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參數(shù)資料
| 型號： | QL2007 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可適應(yīng)性強(qiáng)的3.3V和5.0V pASIC 2系列場可編程邏輯器件) |
| 中文描述： | 3.3V和5.0V帕希奇2 FPGA的結(jié)合速度，密度，低成本和靈活性（高速，高可用密度，低成本，可適應(yīng)性強(qiáng)的3.3和5.0V帕希奇2系列場可編程邏輯器件） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 297K |
| 代理商： | QL2007 |
QL2007
3.3V and 5.0V pASIC
2 FPGA
Combining Speed, Density, Low Cost and Flexibility
3-25
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency
and
performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-7,000 usable ASIC gates, 11,000 usable PLD gates, 174 I/Os
-3-layer metal ViaLink
process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
Other Important Family Features
… 7,000
usable ASICgates,
174 I/O pins
480
Logic
Cells
p
3
QL2007
Block Diagram
Rev. E
pASIC 2
HIGHLIGHTS
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