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參數(shù)資料
| 型號： | Q67126-C2001 |
| 廠商： | SIEMENS AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 28/65頁 |
| 文件大?。?/td> | 427K |
| 代理商： | Q67126-C2001 |
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Semiconductor Group
28
1997-10-01
C540U
C541U
SSC Interface (C541U only)
The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is
compatible to the popular SPI serial bus interface.
Figure 12
shows the block diagram of the SSC.
The central element of the SSC is an 8-bit shift register. The input and the output of this shift register
are each connected via a control logic to the pin P1.3 / SRI (SSC Receiver In) and P1.4 / STO (SSC
Transmitter Out). This shift register can be written to (SFR STB) and can be read through the
Receive Buffer Register SRB.
Figure 12
SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a baud rate
generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is
fully programmable for clock polarity and phase. The pin used for the clock signal is P1.2/ SCLK.
When operating in slave mode, a slave select input is provided which enables the SSC interface
and also will control the transmitter output. The pin used for this is P1.5 / SLS.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
Clock Divider
Clock Selection
Receive Buffer Register
Int. Enable Reg.
Control Register
. . .
f
OSC
Shift Register
STB
SRB
Pin
Control
Logic
Pin
Pin
Pin
Pin
P1.2 / SCLK
P1.3 / SRI
P1.4 / STO
P1.5 / SLS
SCIEN
SSCCON
SCF
Status Register
Control Logic
Interrupt
Internal Bus
MCB03379
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