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| 型號： | Q67121-C967 |
| 廠商： | SIEMENS AG |
| 英文描述： | 16-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 16位CMOS單芯片微控制器 |
| 文件頁數(shù)： | 40/69頁 |
| 文件大?。?/td> | 1124K |
| 代理商： | Q67121-C967 |
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C515C
Semiconductor Group
40
1997-07-01
SSC Interface
The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is
compatible to the popular SPI serial bus interface.
Figure 16
shows the block diagram of the SSC.
The central element of the SSC is an 8-bit shift register. The input and the output of this shift register
are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC
Transmitter Out). This shift register can be written to (SFR STB) and can be read through the
Receive Buffer Register SRB.
Figure 16
SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a baud rate
generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is
fully programmable for clock polarity and phase. The pin used for the clock signal is P4.1/ SCLK.
When operating in slave mode, a slave select input is provided which enables the SSC interface
and also will control the transmitter output. The pin used for this is P4.4 / SLS.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
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