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參數(shù)資料
| 型號： | Q67121-C1070 |
| 廠商： | SIEMENS AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 53/69頁 |
| 文件大?。?/td> | 1124K |
| 代理商： | Q67121-C1070 |
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Semiconductor Group
53
1997-07-01
C515C
–
Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption. The slow down mode can be combined with the idle
mode.
Table 10
gives a general overview of the entry and exit conditions of the power saving modes.
In the power down mode of operation,
V
CC
can be reduced to minimize power consumption. It must
be ensured, however, that
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
is restored to its normal operating level, before the power down mode is terminated.
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C515C.
Table 10
Power Saving Modes Overview
Mode
Entering
(2-Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Software
Power-Down Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Short low pulse at
pin P3.2/INT0
Hardware
Power-Down Mode
HWPD = low
HWPD = high
C515C is put into its reset state
and the oscillator is stopped;
ports become floating outputs
Slow Down Mode
ORL PCON,#10H
ANL PCON,#0EFH
or
Hardware Reset
Oscillator frequency is reduced
to 1/32 of its nominal frequency
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