參數(shù)資料
型號: Q67121-C1068
廠商: SIEMENS AG
元件分類: 8位微控制器
英文描述: 8-Bit CMOS Microcontroller
中文描述: 8位CMOS微控制器
文件頁數(shù): 65/69頁
文件大?。?/td> 1124K
代理商: Q67121-C1068
Semiconductor Group
65
1997-07-01
C515C
Figure 30
SSC Timing
Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid
for the other cases accordingly.
In the case of slave mode and CPHA=0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA=0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
MCT02417
SCLK
STO
SRI
TC
t
SCL
MSB
LSB
MSB
LSB
SCH
t
t
SCLK
S
t
HI
t
~
~
~
~
~
~
D
t
t
HD
DTC
t
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