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參數資料
| 型號： | Q67103-H6594 |
| 廠商： | SIEMENS AG |
| 英文描述： | Memory Time Switch Extended Large MTSXL |
| 中文描述： | 內存定時開關擴展大型MTSXL |
| 文件頁數： | 40/51頁 |
| 文件大?。?/td> | 1052K |
| 代理商： | Q67103-H6594 |
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PEB 2447
Detailed Register Description
Semiconductor Group
40
03.97
4.12
Access in demultiplexed
μ
P-interface mode:
Read/write, address:
Reset value:
Memory Write Data Register High (MWDH)
08
H
XX
H
MWD11..8
Memory Write Data
values (bits 11 to 8); in a write memory access
the values to transfer are written to these registers. Both registers
must not be written during an active access. An active access cycle,
started by a write access to MACH, is indicated by register bit
STAR:MAC.
If the values MWD10..0 / MRD10..0 are used as control memory entries, each possible
value corresponds to a single input time slot. MWD11 / MRD11 defines, whether the
input time slot is switched actively to the PCM output or is switched to high impedance.
Table 13
Input Time Slot Mapping / Programming of Output Tristate Control
TSC
Tristate Control Value
0: active
1: high impedance;
TSC controls whether the output time slot (corresponding to the
address of the control memory location) will drive the PCM values or
will be tristate.
Bit 7
Bit 0
0
0
0
0
MWD11 MWD10 MWD9 MWD8
Mode
MRD11..0 / MWD11..0
Valid for
Inputs/(Ports)
0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IN (31:0) =
Port (31:0)
TSC
Time Slot Number
Port Number
1, 3
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IN (23:16) =
Port (15:8)
IN (7:0) =
Port (7:0)
TSC
Time Slot Number 6..1
PN3 TS0
PN2..0
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