
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
10
12.99
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Operation Mode
CAS Latency
BT
Burst Length
Address Bus (Ax)
Mode Register (Mx)
Operation Mode
BA0
BA1
M8
M10
M11
M9
M7
Mode
burst read /
burst write
0
0
0
0
0
0
0
single write
burst read /
0
0
0
1
0
0
0
Burst Type
M3
Type
Sequential
Interleave
0
1
M6
M5
M4
Latency
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
1
0
1
1
1
0
Reserved
1
1
1
Address Input for Mode Set (Mode Register Operation)
1
1
1
1
0
0
0
0
M2
1
2
Reserved
0
0
1
1
1
0
0
1
1
0
1
1
1
0
0
M1
0
M0
8
4
Length
Burst Length
Sequential
Interleave
Reserved
Full Page*)
1
2
4
8
SPS03409
*) optional