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參數(shù)資料
| 型號： | Q67100-Q1323 |
| 廠商： | SIEMENS AG |
| 英文描述： | 16 MBit Synchronous DRAM |
| 中文描述： | 16兆位同步DRAM |
| 文件頁數(shù)： | 7/53頁 |
| 文件大?。?/td> | 418K |
| 代理商： | Q67100-Q1323 |
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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
7
12.99
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
The System Clock Input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A11
Input
Level
–
During a Bank Activate command cycle, A0 - A11 define
the row address (RA0 - RA11) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0-An define the
column address (CA0 - CAn) when sampled at the rising
clock edge.CAn depends from the SDRAM organization:
16M
×
4 SDRAM CAn = CA9
8M
×
8 SDRAM
CAn = CA8
4M
×
16 SDRAM CAn = CA7
(Page Length = 1024 bits)
(Page Length = 512 bits)
(Page Length = 256 bits)
In addition to the column address, A10 (= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
–
Bank Select Inputs. Selects which bank is to be active.
DQx
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67100-Q1327 | DB25PH |
| Q67100-Q1105 | 2M x 8 - Bit Dynamic RAM 2k Refresh |
| Q67100-Q1106 | DBM13W3S |
| Q67100-Q1107 | 1M x 16-Bit Dynamic RAM 1k & 4k Refresh |
| Q67100-Q1108 | 1M x 16-Bit Dynamic RAM 1k & 4k Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67100-Q1327 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| Q67100-Q1331 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| Q67100-Q1333 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| Q67100-Q1335 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| Q67100-Q1337 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
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