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參數(shù)資料
| 型號： | PZ3128-S10BP |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 161K |
| 代理商： | PZ3128-S10BP |
R
XCR3128: 128 Macrocell CPLD
9
www.xilinx.com
1-800-255-7778
DS034 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Terminations
The CoolRunner XCR3128 CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the lin-
ear region of the CMOS input structures, which can
increase the power consumption of the device. The
XCR3128 CPLDs have programmable on-chip pull-down
resistors on each I/O pin. These pull-downs are automati-
cally activated by the fitter software for all unused I/O pins.
Note that an I/O macrocell used as buried logic that does
not have the I/O pin used for input is considered to be
unused, and the pull-down resistors will be turned on. We
recommend that any unused I/O pins on the XCR3128
device be left unconnected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10k
pull-up resistors. These pins can be directly connected to
V
CC
or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10k
pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Let-
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes
JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs
and
Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs
for more informa-
tion.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD
’
s and other integrated cir-
cuits. The Xilinx XCR3128 supports the following methods:
PC parallel port
Workstation or PC serial port
Embedded processor
Automated test equipment
Third party programmers
High-End JTAG and ISP tools
A Boundary-Scan Description Language (BSDL) descrip-
tion of the XCR3128 is also available from Xilinx for use in
test program development. For more details on JTAG and
ISP for the XCR3128, refer to the related application note:
JTAG and ISP Overview for Xilinx XPLA1 and XPLA2
CPLDs
.
Table 5: Programming Specifications
Symbol
DC Parameters
V
CCP
I
CCP
V
IH
V
IL
V
SOL
V
SOH
TDO_I
OL
TDO_I
OH
AC Parameters
f
MAX
PWE
PWP
PWV
INIT
TMS_SU
TDI_SU
TMS_H
TDI_H
TDO_CO
Parameter
Min.
Max.
Unit
V
CC
supply program/verify
I
CC
limit program/verify
Input voltage (High)
Input voltage (Low)
Output voltage (Low)
Output voltage (High)
Output current (Low)
Output current (High)
3.0
3.6
200
V
mA
V
V
V
V
mA
mA
2.0
0.8
0.5
2.4
8
-8
CLK maximum frequency
Pulse width erase
Pulse width program
Pulse width verify
Initialization time
TMS setup time before TCK
=
TDI setup time before TCK
=
TMS hold time after TCK
=
TDI hold time after TCK
=
TDO valid after TCK
Ο
10
100
10
10
100
10
10
25
25
MHz
ms
ms
μ
s
μ
s
ns
ns
ns
ns
ns
40
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