參數(shù)資料
型號(hào)： PZ3064-12BB1
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： PLD
英文描述： Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:8; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight
中文描述： EE PLD, 14.5 ns, PQFP100
封裝： 14 X 20 X 2.80 MM, PLASTIC, SOT-382-1, QFP-100
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 245K
代理商： PZ3064-12BB1
Philips Semiconductors
Product specification
PZ3064
64 macrocell CPLD
1997 Mar 05
86
Simple Timing Model
Figure 4 shows the CoolRunner
Timing Model. The CoolRunner
timing model looks very much like a 22V10 timing model in that
there are three main timing parameters, including t
PD
, t
SU
, and t
CO
.
In other competing architectures, the user may be able to fit the
design into the CPLD, but is not sure whether system timing
requirements can be met until after the design has been fit into the
device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing channels
used, etc. In the XPLA
architecture, the user knows up front
whether the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in the
PZ3064 device, the user knows up front that if a given output uses
5 product terms or less, the t
PD
= 10ns, the t
SU_PAL
= 6ns, and the
t
CO
= 7ns. If an output is using 6 to 37 product terms, an additional
2ns must be added to the t
PD
and t
SU
timing parameters to account
for the time to propagate through the PLA array.
TotalCMOS
Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS
CPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer CPLDs which are both high performance and
low power, breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 5 and Table 2 showing the I
DD
vs. Frequency of our PZ3064 TotalCMOS
CPLD.
OUTPUT PIN
INPUT PIN
SP00441
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
CLOCK
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
Figure 4.
CoolRunner
Timing Model
TYPICAL
I
(mA)
FREQUENCY (MHz)
SP00460A
0
20
40
60
80
100
0
20
40
60
80
100
Figure 5.
I
DD
vs. Frequency @ V
DD
= 3.3V, 25
°
C
Table 2. I
DD
vs. Frequency
V
DD
= 3.3V
FREQUENCY (MHz)
0
20
40
60
80
100
Typical I
DD
( mA)
0.04
13
26
40
50
63
相關(guān)PDF資料
PDF描述
PZ3064-12BC Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight
PZ3064-10BB1-S RF inductor, ferrite core, 2% tol, SMT, RoHS
PZ3064-10BC-S Electrically-Erasable Complex PLD
PZ3064-12BB Electrically-Erasable Complex PLD
PZ3064-12BB1-S Electrically-Erasable Complex PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PZ3064-12BB1-S 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD
PZ3064-12BC 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:64 macrocell CPLD
PZ3064-12BC-S 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD
PZ3064AS10A44 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD
PZ3064AS10BC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD
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