參數(shù)資料
型號(hào)： PXAG37
廠商： NXP Semiconductors N.V.
英文描述： XA 16-bit microcontroller family(XA16位微控制器系列)
中文描述： 的XA 16位微控制器系列（XA16位微控制器系列）
文件頁(yè)數(shù)： 24/36頁(yè)
文件大?。?/td> 208K
代理商： PXAG37
Philips Semiconductors
Product specification
XA-G3
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
1999 Apr 07
24
AC ELECTRICAL CHARACTERISTICS (3V)
V
DD
= 2.7V to 5.5V; T
amb
= 0 to +70
°
C for commercial, –40
°
C to +85
°
C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
Address Cycle
t
CRAR
t
LHLL
t
AVLL
t
LLAX
Code Read Cycle
21
Delay from clock rising edge to ALE rising edge
15
60
ns
16
ALE pulse width (programmable)
(V1 * t
C
) – 10
(V1 * t
C
) – 18
(t
C
/2) – 12
ns
16
Address valid to ALE de-asserted (set-up)
ns
16
Address hold after ALE de-asserted
ns
t
PLPH
t
LLPL
t
AVIVA
t
AVIVB
t
PLIV
t
PXIX
t
PXIZ
t
IXUA
Data Read Cycle
16
PSEN pulse width
(V2 * t
C
) – 12
(t
C
/2) – 9
ns
16
ALE de-asserted to PSEN asserted
ns
16
Address valid to instruction valid, ALE cycle (access time)
(V3 * t
C
) – 58
(V4 * t
C
) – 52
(V2 * t
C
) – 52
ns
17
Address valid to instruction valid, non-ALE cycle (access time)
ns
16
PSEN asserted to instruction valid (enable time)
ns
16
Instruction hold after PSEN de-asserted
0
ns
16
Bus 3-State after PSEN de-asserted (disable time)
t
C
– 8
ns
16
Hold time of unlatched part of address after instruction latched
0
ns
t
RLRH
t
LLRL
t
AVDVA
t
AVDVB
t
RLDV
t
RHDX
t
RHDZ
t
DXUA
Data Write Cycle
18
RD pulse width
(V7 * t
C
) – 12
(t
C
/2) – 9
ns
18
ALE de-asserted to RD asserted
ns
18
Address valid to data input valid, ALE cycle (access time)
(V6 * t
C
) – 58
(V5 * t
C
) – 52
(V7 * t
C
) – 52
ns
19
Address valid to data input valid, non-ALE cycle (access time)
ns
18
RD low to valid data in, enable time
ns
18
Data hold time after RD de-asserted
0
ns
18
Bus 3-State after RD de-asserted (disable time)
t
C
– 8
ns
18
Hold time of unlatched part of address after data latched
0
ns
t
WLWH
t
LLWL
t
QVWX
t
WHQX
t
AVWL
t
UAWH
Wait Input
20
WR pulse width
(V8 * t
C
) – 12
(V12 * t
C
) – 10
(V13 * t
C
) – 28
(V11 * t
C
) – 8
(V9 * t
C
) – 28
(V11 * t
C
) – 10
ns
20
ALE falling edge to WR asserted
ns
20
Data valid before WR asserted (data setup time)
ns
20
Data hold time after WR de-asserted (Note 6)
ns
20
Address valid to WR asserted (address setup time) (Note 5)
ns
20
Hold time of unlatched part of address after WR is de-asserted
ns
t
WTH
t
WTL
21
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * t
C
) – 40
ns
21
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
(V10 * t
C
) – 5
ns
NOTES:
1. Load capacitance for all outputs = 80pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).
Refer to the XA User Guidefor details of the bus timing settings.
V1)
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2)
This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
–
For a bus cycle with
no
ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst
mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
–
For a bus cycle
with
an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10,
and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5).
Example:
If CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.
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