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參數(shù)資料
| 型號(hào)： | PXAC37KFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller family(16位微控制器系列) |
| 中文描述： | 16-BIT, OTPROM, 32 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 45/68頁(yè) |
| 文件大?。?/td> | 344K |
| 代理商： | PXAC37KFA |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
38
Location of Sample Point
The location of the sample point within a bit period is determined
according to the following:
one bit period
tSYNC–
SEG
tSEG1
tSEG2
Sample point
SU01339
tSYNCSEG = tSCL
tSEG1 = tSCL
(8
tSEG1.3 + 4
tSEG1.2 + 2
tSEG1.1 +
tSEG1.0 + 1)
tSEG2 = tSCL
(4
tSEG2.2 + 2
tSEG2.1 + tSEG2.0 + 1)
where tSEG1.3 – tSEG1.0 and tSEG2.2 – tSEG2.0 are bits in
CANBTR.
Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different
bus controllers, any bus controller must re–synchronize on any
relevant signal edge of the current transmission. The
Synchronization Jump Width defines the maximum number of CAN
System Clock cycles that a bit period may be shortened or
lengthened by one re–synchronization, and is given by the following
expression:
tSJW = tSCL
(2
SJW.1 + SJW.0 + 1)
where SJW.1 and SJW.0 are bits in CANBTR.
CANBTR: CAN Bus Timing Register
Address: MMR base + 272h
Access: Read, Write during reset mode only. Word access only.
Reset value: 0000h
CANBTR
15
SAM
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
CAN Command and Status Registers
Two Modes in CAN Core Operation
The CCB has two different modes of operation: Reset mode, and
Operation mode. On hardware reset, the CAN core is in Reset
mode, and the RR bit of CANCMR (
CAN
C
o
m
mand
R
egister) will
be set. The User application would usually set up registers, etc.,
then put the CCB into Operation mode by clearing the RR bit.
While in Operation mode, the following conditions will cause the RR
bit to be set, putting the CCB back into Reset mode:
Tx Buffer Underflow (TBUF)
Bus Off
Hardware reset
Test mode (Refer to XA-C3 User Guide, Sections 2.2.2.1 and
2.7.1.2)
CANCMR: CAN Command Register
Address: MMR base + 270h
Access: Read/Write, no R/M/W, Byte or Word Access. Hardware
can set bit 0.
Reset value: 01h
CANCMR
7
6
5
4
3
2
1
0
RXP
ST
LO
Reserved
SLPEN
OC1
Reserved
RR
RXP
Rx Polarity, writable during reset mode only.
0 = non–inverted, 1 = inverted.
Self test, disable TxACK
Listen only
Reserved bit.
CTL will go back to idle if no interrupt is
generated.
Output control for Tx pad. 0 = Push–Pull,
1 = Open Drain
ST
LO
Reserved
SLPEN
OC1
Reserved
RR
Reserved bit
Reset Request.
CANSTR: CAN Status Register
Address: MMR base + 271h
Access: Read only, no write, no R/M/W. Byte access OK.
Hardware can set or clear bits 7 – 2.
Reset value: 00h
CANSTR
7
6
5
4
3
2
1
–
0
–
BS
EP
EW
TS
RS
SLPOK
BS
EP
EW
TS
Bus status
Error passive
Error warning
Transmit status
RS
SLPOK
Receive status
CAN status: no CAN bus activity and no
pending core interrupts
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