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參數(shù)資料
| 型號： | PWS726A |
| 英文描述： | Isolated, Unregulated DC/DC CONVERTERS |
| 中文描述： | 隔離，穩(wěn)壓DC / DC轉換器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 68K |
| 代理商： | PWS726A |
4
PWS725A/726A
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
°
C, V
CC
=
±
15VDC unless otherwise noted.
THEORY OF OPERATION
The PWS725A and the PWS726A DC/DC converters con-
sist of a free-running oscillator, control and switch driver
circuitry, MOSFET switches, a transformer, a bridge recti-
fier, and filter capacitors together in a 32-pin DIP (0.900
inches nominal) package. The control circuitry consists of
current limiting, soft start, frequency adjust, enable, and
synchronization features. See Figure 1. In instances where
several converters are used in a system, beat frequencies
developed between the converters are a potential source of
low frequency noise in the supply and ground paths. This
noise may couple into signal paths. See Figures 2 and 3 for
connection of INPUT SYNC pin. Converters can be syn-
FIGURE 1. PWS725A/726A Functional Diagram.
chronized and these beat frequencies avoided. The unit with
the highest natural frequency will determine the synchro-
nized running frequency. To avoid excess stray capaci-
tance, the INPUT SYNC pin should not be loaded with
more than 50pF. If unused, the INPUT SYNC must be left
open.
Soft start circuitry protects the MOSFET switches during
start up. This is accomplished by holding the gate-to-source
voltage of both MOSFET switches low until the free-
running oscillator is fully operational. In addition to that
soft start circuitry, input current sensing also protects the
MOSFET switches. This current limiting keeps the FET
Full-Wave
Bridge
Rectifier
L
L
Oscillator/
Driver
Control
R
SC
20
19
20k
18
15
14
16
L
IN
(5)
V
IN
7-18/VDC
C
IN
(5)
Frequence
Increase
ENABLE
(3)
INPUT
SYNC
(2)
0.22μF
0.22μF
0.22μF
L
O
(4)
L
O
(4)
32
1
4 & 30
C
O
(4)
C
O
(4)
+
–
+
–
+V
OUT
–V
OUT
+I
O
–I
O
29
OUTPUT SYNC
(1) Frequency Adjust is optional, with pins 19 and 20 left open. The normal switching frequency is 800kHz.
(2) Leave INPUT SYNC pin open if unused; limit stray capacitance on INPUT SYNC pin to less than 50pF.
(3) Leave ENABLE pin open or connect to V
IN
if not used.
(4) Optional output filtering, with L
O
= 0, limit C
O
≤
1μF, with L
O
= 100μH, limit C
O
≤
10μF, see Performance
Curves for L
= 0.
(5) Optional input filtering, see Performance Curves for L
= 0.
(6) CAUTION: Do not connect pin 29 to low impedance loads. See Figure 5.
NOTES:
SYNC FREQUENCY vs
INPUT CURRENT AND OUTPUT VOLTAGE
SYNC Frequency (kHz)
(Optional External Control)
O
400
15
14
800
1200
1600
90
80
70
60
I
V
IN
= +15V
±V
OUT
I
INPUT
(I
O
= ±15mA)
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