參數(shù)資料
型號: PUMA77S16000M-55
英文描述: 20NS, 44 PLCC, COM TEMP(EPLD)
中文描述: X32號的SRAM模塊
文件頁數(shù): 4/10頁
文件大?。?/td> 196K
代理商: PUMA77S16000M-55
PUMA 2/77S16000 - 020/025/35
ISSUE 4.3 April 2001
3
Operating Modes
The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
device.
Mode
CS
OE
WE
V
CC Current
I/O Pin
Reference Cycle
Not Selected
1
X
I
SB1,ISB2
High Z
Power Down
Output Disable
0
1
I
CC
High Z
Read
0
1
I
CC
D
OUT
Read cycle
Write
0
X
0
I
CC
D
IN
Write Cycle
Note: CS above is accessed through CS1~4 and WE is accessed through WE1~4. For correct operation, CS1~ 4 and
WE1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.
1 = V
IH,
0 = V
IL,
X = Don't Care
166
30pF
I/O Pin
1.76V
AC Test Conditions
Output Load
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*V
cc=5V±10%
*PUMA module is tested in 32 bit mode.
Capacitance (V
CC=5V±10%,TA=25°C)
Note: These parameters are calculated and not measured.
Parameter
Symbol
Test Condition
typ
max
Unit
Input Capacitance Address, OE
C
IN1
V
IN =0V
-
34
pF
WE1~4, CS1~4
C
IN2
V
IN =0V
-
6
pF
I/O Capacitance
D0~31
C
I/O
V
I/O=0V
-
42
pF (8 bit mode)
相關(guān)PDF資料
PDF描述
PUMA77S16000MB-020 20NS, 68 PLCC, COM TEMP(EPLD)
PUMA77S16000MB-025 20NS, 44 PLCC, IND TEMP(EPLD)
PUMA77S16000MB-35 x32 SRAM Module
PUMA77S16000MB-45 x32 SRAM Module
PUMA77S16000MB-55 x32 SRAM Module
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