參數(shù)資料
型號: PUMA2S1000M-35
元件分類: SRAM
英文描述: 32K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CHMA66
封裝: CERAMIC, MODULE, PGA-66
文件頁數(shù): 5/9頁
文件大小: 555K
代理商: PUMA2S1000M-35
PUMA 2S1000 - 25/35/45
ISSUE 4.5 : August 2002
5
Read Cycle 1 Timing Waveform (1)
Notes: (1) WE1~4 is High for Read Cycle.
(2) Device is continuously selected, CS1~4=V
IL.
(3) t
CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
(4) OE=V
IL.
Read Cycle 2 Timing Waveform (1) (2) (4)
t
RC
AA
OE
OH
Address
OE
CS1~4
t OHZ(3)
t OLZ
t
ACS
t CLZ
t CHZ(3)
Data Valid
Dout
High-Z
t RC
t AA
t OH
Data Valid
Address
Dout
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