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參數(shù)資料
| 型號(hào)： | PUCC3801T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | Current-mode PWM controller |
| 中文描述： | SWITCHING CONTROLLER, 100 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, SOT-96, 8 PIN |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 308K |
| 代理商： | PUCC3801T |
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Philips Semiconductors
PUCC3801
Current-mode PWM controller
Product data
Rev. 01 — 10 September 2001
6 of 16
9397 750 08419
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
When V
DD
rises above 10 V, V
REG
rises to 6 V and the operating supply current
increases to typically 1.2 mA. The device starts normal operation and output pulses
are produced.
The over-voltage trip sequence is initiated if V
DD
rises above 14 V. When this
happens, the output pulses are disabled, V
REG
is reduced gradually to 3 V, and the
output of the over-voltage latch goes HIGH.
The device remains in the over-voltage lockout mode until V
DD
falls below 5 V.
Input voltage clamp:
V
DD
is clamped to a maximum of 16.5 V. The size of the
external resistor must be sufficient to ensure that the current into the V
DD
pin never
exceeds 15 mA.
7.2.2
Controller section
Oscillator:
The internal oscillator generates a 75% duty cycle digital clock to the
output latch, and a 100 kHz voltage ramp to the PWM circuit. The frequency is
modulated by approximately 20% by a Pseudo Random Binary Sequence (PRBS)
that repeats every 15 cycles. This spreads the electromagnetic interference produced
by the power supply over a narrow band of frequencies centered on 100 kHz. This
reduces the amplitude of the harmonics in the interference spectrum.
Error amplifier:
This section senses one of the various feedback methods used to
control the output duty cycle. It contains an operational transconductance amplifier
(ERRAMP), that can be externally compensated at the COMP pin. The reference
input of ERRAMP is connected to a 2.5 V reference voltage. The FB input is internally
connected to a voltage divider from V
DD
. If the FB pin is not connected, the device will
tend to regulate V
DD
to 12 V.
The output of the error amplifier is connected to the PWM section by a voltage divider
with a gain of 0.4 and an output impedance of 100 k
.
PWM:
The PWM section includes a current sense input from the CSNS pin, a
low-pass filter, summing amplifier, a high-speed comparator and logic. This section
sums the analog ramp from the oscillator with the voltage on the CSNS pin. This
signal is fed to a comparator that triggers on the falling edge of the PWM clock signal.
This provides line compensation and load regulation. The internal slope
compensation function removes the need for external components to generate a
ramp signal that is added to the current sense signal.
A fast over-current path is provided from CSNS to OUT with a typical propagation
delay of 170 ns.
Output driver:
This section is a high-speed, high-current output stage capable of
driving the gate of a large power FET. Typical rise and fall times are 160 ns and
150 ns respectively into a 2 nF load.
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