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參數(shù)資料
| 型號： | PTN3310 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High-speed serial logic translators |
| 中文描述： | 高速串行邏輯翻譯 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 62K |
| 代理商： | PTN3310 |
Philips Semiconductors
Product data
PTN3310/PTN3311
High-speed serial logic translators
2001 Jun 19
5
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
General
f
MAX
Maximum throughput data rate
655
800
–
Mbps
t
S
Clock output skew, part-to-part
–
100
–
ps
Clock output pulse skew
–
50
–
ps
t
PLH
PHL
/t
Propagation delay input (differential) to output
–
1
3
ns
Propagation delay input (single-ended) to output
–
1
3
ns
PECL outputs (PTN3310)
t
r
/t
f
Output rise and fall times at 20% and 80%
intersects
LVDS outputs (PTN3311); R
L
= 100
; C
L
= 5 pF
t
TLH
Transition time LOW to HIGH
t
THL
Transition time HIGH to LOW
–
200
300
ps
R
L
= 100
; C
L
= 5 pF
R
L
= 100
; C
L
= 5 pF
Measured between two
matched 49.9
load resistors;
5 pF load capacitance
–
500
650
ps
–
500
650
ps
V
OSS
Peak-to-peak switching offset voltage
–
–
150
mV
LVDS REFERENCE MEASUREMENT CONFIGURATION
ST00041
PTN331x
1 5
2 6
3 7
4 8
C
LVDS
R
load
R
load
Vos
Voutp
C
probe
C
probe
Voutn
Vod = Voutp – Voutn
R
load
= 50 Ohms
C
LVDS
= 5 pF
The above diagram shows the test set-up used when evaluating
LVDS outputs. According to the TIA-EIA-644 Standard, the
maximum lumped capacitance test load should be 5 pF. However,
by using probes or cables to observe the signal, additional
capacitance is added, which has an effect on the rise and fall times.
C
probe
represents any capacitance caused by the use of probes or
cables. Assuming balanced loading and balanced output drivers, the
total effective capacitance seen by the part is:
C
Eff
= C
LVDS
+
1
/
2
C
probe
To correctly account for the effects of C
probe
, the following formula
should be used:
t
5 pF
C
Eff
t
measured,
Where
t is the 20%–80% rise/fall time.
To avoid the use of additional calculation of the measured results, a
different approach could be taken; however, the value of C
probe
has
to be known in advance. In that case, the value of C
LVDS
can be
chosen such that the sum of the capacitances equals 5 pF, i.e.:
C
LVDS
+
1
/
2
C
probe
= 5 pF
相關PDF資料 |
PDF描述 |
|---|---|
| PTN3311 | High-speed serial logic translators |
| PTN3311D | High-speed serial logic translators |
| PTN3500 | Maintenance and control device |
| PTN3500D | Maintenance and control device |
| PTN3500DH | Maintenance and control device |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PTN3310_04 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed serial logic translators |
| PTN3310D | 功能描述:轉換 - 電壓電平 LVDS-PECL LOGIC TRANSLATOR RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| PTN3310D,112 | 功能描述:轉換 - 電壓電平 LVDS-PECL LOGIC RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| PTN3310D,118 | 功能描述:轉換 - 電壓電平 LVDS-PECL LOGIC RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| PTN3310DP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed serial logic translators |
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