
TM1300 Data Book
Philips Semiconductors
A-58
PRODUCT SPECIFICATION
IEEE status flags from floating-point sign
SYNTAX
[ IF rguard ] fsignflags rsrc1
→
rdest
FUNCTION
if
rguard
then
rdest
←
ieee_flags(sign((float)rsrc1))
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fcomp
153
1
No
—
1
3
DESCRIPTION
The
fsignflags
operation computes the IEEE exceptions that would result from computing the sign of rsrc1 and
stores a bit vector representing the exception flags into rdest The argument value is in IEEE single-precision floating-
point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If the argument is
denormalized, zero is substituted before computing the sign, and the IFZ bit in the result is set.
The
fsignflags
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x40400000 (3.0)
r40 = 0xbf800000 (-1.0)
r50 = 0x80800000 (-1.175494351e-38)
r60 = 0x80400000 (-5.877471754e-39)
r10 = 0, r70 = 0xffffffff (QNaN)
r20 = 1, r70 = 0xffffffff (QNaN)
r80 = 0xff800000 (-INF)
fsignflags r30
→
r100
fsignflags r40
→
r105
fsignflags r50
→
r110
fsignflags r60
→
r115
IF r10 fsignflags r70
→
r116
IF r20 fsignflags r70
→
r117
fsignflags r80
→
r120
r100
←
0
r105
←
0
r110
←
0
r115
←
0x20 (IFZ)
no change, since guard is false
r117
←
0x10 (INV)
r120
←
0
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
0
31
0
SEE ALSO
fsign readpcsw
fsignflags