參數(shù)資料
型號: PT6933N
廠商: Texas Instruments, Inc.
英文描述: 100V Single N-Channel HEXFET Power MOSFET in a D2-Pak package; A IRF3710S with Standard Packaging
中文描述: 模擬IC
文件頁數(shù): 1/7頁
文件大?。?/td> 159K
代理商: PT6933N
For technical support and more information, see inside back cover or visit www.ti.com
PT6930 Series
Standard Application
8-A 5V-Input Dual-Output
Integrated Switching Regulator
Ordering Information
PT 6931
= +3.3 Volts
+2.5/1.8 Volts
PT 6932
= +3.3 Volts
+1.5/1.2 Volts
PT 6933
= +3.3 Volts
+1.8/1.2 Volts
C
1
/C
2
=Req’d 330μF electrolytic (See table footnotes)
=Optional 100μF electrolytic
C
3
Features
Dual Outputs:
+3.3V/2.5V
+3.3V/1.5V
+3.3V/1.8V
Adjustable Output Voltages
Remote Sense (both outputs)
Standby Function
Over-Temperature Protection
Soft-Start
Internal Sequencing
23-pin Excalibur Package
Pin Function
1
Vo
1
Sense
2
No Connect
3
STBY
4
V
IN
5
V
IN
6
V
IN
7
GND
8
GND
9
GND
10
GND
11
GND
12
Vo
1
Pin
13
14
15
16
17
18
19
20
21
22
23
Function
Vo
1
Vo
1
Vo
1
Vo
1
Adjust
No Connect
Vo
2
Vo
2
Vo
2
Vo
2
Vo
2
Sense
Vo
2
Adjust
*
Pin-Out Information
Description
The PT6930 Excalibur series of 8-A
dual-output ISRs are designed to power
DSP ICs. Both output voltages are inde-
pendently adjustable with external resistors.
The second output may also be set to an
alternate lower bus voltage with a simple
pin strap. Internal power sequencing of
both outputs, during both power-up and
power-down, meets the requirements of
most DSP chipsets.
PT6930
C
2
+
GND
V
IN
GND
4,5,6
7-11
12-15
18-21
16
C
1
22
C
3
+
23
1
3
STBY
Vo
2
Sense
Vo
1
Sense
Vo
1
Vo
2
PT Series Suffix
(PT1234
X
)
Case/Pin
Configuration
Vertical Through-Hole
Horizontal Through-Hole
Horizontal Surface Mount
(For dimensions and PC board layout, see
Package Styles 1320 and 1330).
N
A
C
SLTS062B
(Revised 7/20/2001)
* Note:Vo
& Vo
Adjust can be pin-strapped to an
alternative lower bus voltage. Consult the voltage
adjustment application note for more information.
Specifications
Characteristics
(T
a
= 25°C unless noted)
Output Current
PT6930 SERIES
Typ
Symbols
Io
1
, Io
2
Conditions
T
a
=
+60°C, 200 LFM, pkg N
Min
0.1
(1)
0
0
0
0
0.1
(1)
0
0
0
0
4.5
Max
5.5
(2)
2.2
(2)
1.75
(2)
1.45
(2)
1.2
(2)
6.0
(2)
2.2
(2)
1.75
(2)
1.45
(2)
1.2
5.5
Units
Vo
1
=3.3V
Vo
2
=2.5V
Vo
2
=1.8V
Vo
2
=1.5V
Vo
1
=1.2V
Vo
1
=3.3V
Vo
2
=2.5V
Vo
2
=1.8V
Vo
2
=1.5V
Vo
1
=1.2V
A
T
a
=
+25°C, natural convection
A
A
(2)
Input Voltage Range
Output Voltage Tolerance
V
in
V
o
0.1A
I
o
I
typ
V
= +5V, I
=I
typ,
both outputs
0°C
T
a
+65°C
4.5V
V
in
5.5V, I
o
=I
typ
V
V
o
-0.1
V
o
+0.1
V
Line Regulation
Reg
line
Vo
1
Vo
2
Vo
1
Vo
2
Vo
1
Vo
2
±7
±7
±17
±4
50
25
25
60
60
75
±17
±13
±33
±10
V
Load Regulation
Reg
load
V
in
= +5V, 0.1
I
o
I
typ
mV
V
o
Ripple/Noise
V
n
V
in
= +5V, I
o
=I
typ
mV
Transient Response
with C
2
= 330μF
t
tr
V
os
I
o
step between 0.5xI
typ
and I
typ
V
o
over/undershoot
μSec
mV
Vo
1
Vo
2
Efficiency
Switching Frequency
η
o
V
in
= +5V, I
o
=4A total
4.5V
V
in
5.5V
0.1A
I
o
I
typ
%
475
600
725
kHz
(Continued)
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