- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383786 > PSD954F2V-90M (意法半導(dǎo)體) Flash In-System Programmable ISP Peripherals For 8-bit MCUs PDF資料下載
參數(shù)資料
| 型號： | PSD954F2V-90M |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁數(shù)： | 37/94頁 |
| 文件大?。?/td> | 476K |
| 代理商： | PSD954F2V-90M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
Preliminary Information
PSD9XX Family
33
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 10, is used for decoding the address for internal PSD
components. The DPLD can generate the following chip selects:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the Secondary Flash memory (three product terms each)
1 internal SRAM select (two product terms)
1 internal CSIOP select (select PSD registers, one product term)
Inputs to the DPLD chip selects may include address inputs, Page Register inputs and
other user defined external inputs from Ports A, B, C or D.
9.2.2 General Purpose PLD (GPLD)
The General Purpose PLD implements user defined system combinatorial logic function
or chip selects for external devices. Figure 11 shows how the GPLD is connected to the
I/O Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can
also be configured as input tot eh GPLD. When it is not used as GPLD output or input, the
pin can be configured to perform other I/O functions.
The GPLD outputs are identical except in the number of available product terms for logic
implementation. Select the pin that can best meet the product term requirement of your
logic function or chip selects. The outputs can be configured as active high or low outputs.
Table 16 shows the number of product terms that are assigned to the PLD outputs on the
I/O Ports. When PSD9XX is connected to a MCU with non-multiplexed bus, Port A will be
configured as the Data Port and the GPLD outputs will not be available.
The
PSD9XX
Functional
Blocks
(cont.)
GPLD Output on Port Pin
Number of Product Terms
Port A, pins PA0-3
Port A, pins PA4-7
Port B, pins PB0-3
Port B, pins PB4-7
Port D, pins PD0-2
3
9
4
7
1
Table 16. GPLD Output Product Term
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD954F2V-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2 | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2-70J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2-70M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD934F2-90J | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PS-DA0104-01 | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0104-01S | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0105-01 | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0105-01S | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
| PS-DA0105-03 | 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。