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    參數(shù)資料
    型號(hào): PSD9545V70MIT
    廠商: 意法半導(dǎo)體
    元件分類: 基準(zhǔn)電壓源/電流源
    英文描述: Advanced PFC/PWM Combination Controllers 20-PDIP -40 to 105
    中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
    文件頁(yè)數(shù): 71/110頁(yè)
    文件大?。?/td> 1737K
    代理商: PSD9545V70MIT
    71/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    INITIAL DELIVERY STATE
    When delivered from ST, the PSD device has all
    bits in the memory and PLDs set to ’1.’ The PSD
    Configuration Register bits are set to ’0.’ The code,
    configuration, and PLD logic are loaded using the
    programming procedure. Information for program-
    ming the device is available directly from ST.
    Please contact your local sales representative.
    Table 35. JTAG Enable Register
    Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-
    uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is
    used to enable the JTAG signals.
    Bit 0
    JTAG_Enable
    0 = off JTAG port is disabled.
    1 = on JTAG port is enabled.
    Bit 1
    X
    0
    Not used, and should be set to zero.
    Bit 2
    X
    0
    Not used, and should be set to zero.
    Bit 3
    X
    0
    Not used, and should be set to zero.
    Bit 4
    X
    0
    Not used, and should be set to zero.
    Bit 5
    X
    0
    Not used, and should be set to zero.
    Bit 6
    X
    0
    Not used, and should be set to zero.
    Bit 7
    X
    0
    Not used, and should be set to zero.
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