- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368296 > PSD935G1V-70J (意法半導(dǎo)體) Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 39pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate PDF資料下載
參數(shù)資料
| 型號： | PSD935G1V-70J |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 39pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| 中文描述： | 在8片位微控制器可配置存儲系統(tǒng) |
| 文件頁數(shù)： | 38/91頁 |
| 文件大?。?/td> | 488K |
| 代理商： | PSD935G1V-70J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁
PSD935G2
PSD9XX Family
37
The
PSD935G2
Functional
Blocks
(cont.)
9.3 Microcontroller Bus Interface
The
“
no-glue logic
”
PSD935G2 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 14. The MCU interface type is
specified using the PSDsoft.
9.3.1. PSD935G2 Interface to a Multiplexed Bus
Figure 13 shows an example of a system using a microcontroller with a 8-bit multiplexed
bus and a PSD935G2. The ADIO port on the PSD935G2 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port E, F or G. The PSD935G2 drives the ADIO data bus
only when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional
address inputs.
9.3.2. PSD935G2 Interface to a Non-Multiplexed Bus
Figure 14 shows an example of a system using a microcontroller with a 8-bit
non-multiplexed bus and a PSD935G2. The address bus is connected to the ADIO Port,
and the data bus is connected to Port F. Port F is in tri-state mode when the PSD935G2
is not accessed by the microcontroller. Should the system address bus exceed sixteen
bits, Ports A, B or C may be used for additional address inputs.
Data
Bus
Width
MCU
CNTL0
CNTL1
CNTL2
PC7
*
*
*
*
*
*
*
DBE
*
*
*
*
PD0**
ADIO0
PF3-PF0 PF7-PF4
*
A3-A0
*
*
*
*
*
*
D3-D0
*
*
D3-D0
8031/8051
80C51XA
80C251
80C251
80198
68HC11
68HC05C0
68HC912
Z80
Z8
68330
M37702M2
8
8
8
8
8
8
8
8
8
8
8
8
WR
WR
WR
WR
WR
R/W
WR
R/W
WR
R/W
R/W
R/W
RD
RD
PSEN
RD
RD
E
RD
E
RD
DS
DS
E
PSEN
PSEN
*
PSEN
*
*
*
*
*
*
*
*
ALE
ALE
ALE
ALE
ALE
AS
AS
AS
*
AS
AS
ALE
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
*
*
*
*
*
*
*
*
D7-D4
*
*
D7-D4
Table 14. Microcontrollers and their Control Signals
*
*
Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-0, PA3-0) can be
**
configured for other I/O functions.
**
ALE/AS input is optional for microcontrollers with a non-multiplexed bus
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD935G1V-70JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935G1V-70M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935G1V-70MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935G1V-70U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935G1V-70UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD935G2-90U | 功能描述:SPLD - 簡單可編程邏輯器件 TQFP-80 5V 4M 90N RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD935G2V-90U | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD835G2V-90U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD954F2-90J | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD954F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD954F2V-90J | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。