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      參數(shù)資料
      

      


      


      
型號(hào)：
PSD935F2V-C-20JI

      

      
廠商：
意法半導(dǎo)體

      

      
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

      

      
文件頁(yè)數(shù)：
49/91頁(yè)

      

      
文件大?。?/td>
488K

      

      
代理商：
PSD935F2V-C-20JI


      

      

      

	
      
    
    

    
      
	
      PSD9XX Family 
      PSD935G2
      48
      Control
      Register
      Setting
      Direction
      Register
      Setting
      VM
      Defined In
      PSDsoft
      Register
      Setting
      Mode
      Declare
      pins only
      0
      1= output,
      0= input
      MCU I/O
      (Note 1)
      NA
      Declare pins 
      and logic or chip
      select equations
      PLD I/O
      NA
      NA
      Data Port
      (Port F)
      Selected for
      MCU with 
      non-mux bus
      NA
      NA
      NA
      Address Out
      (Port E, F, G)
      Declare
      pins only
      1
      1
      NA
      Address In
      (Port A,B,C,D,F)
      Declare pins
      NA
      NA
      NA
      JTAG ISP
      Declare pins
      only
      NA
      NA
      NA
      Table 17.  Port Operating Mode Settings
      *
      NA = Not Applicable
      NOTE:
       1. Control Register setting is not applicable to Ports A, B and C.
      9.4.2.1   MCU I/OMode
      In the MCU I/O Mode, the microcontroller uses the PSD935G2 ports to expand its own 
      I/O ports. By setting up the CSIOP space, the ports on the PSD935G2 are mapped into the
      microcontroller address space. The addresses of the ports are listed in Table 6.
      A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
      Control Register (Port E, F and G). The MCU I/O direction may be changed by writing 
      to the corresponding bit in the Direction Register. See the subsection on the Direction
      Register in the “Port Registers” section. When the pin is configured as an output, the 
      content of the Data Out Register drives the pin. When configured as an input, the 
      microcontroller can read the port input through the Data In buffer. See Figure 20.
      Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
      They can be used for PLD I/O if they are specified in PSDsoft.
      9.4.2.2   PLD I/OMode
      The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro
      Cells, and/or 
      as an output from the GPLD. The corresponding bit in the Direction Register must not be
      set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified
      in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.
      The 
      PSD935G2
      Functional
      Blocks
      (cont.)
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
PSD935F2V-C-20M
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD935F2V-C-20MI
Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 2700pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080&quot; x 0.050&quot; x 0.055&quot;; Container: Bag; Features: MIL-PRF-55681: M Failure Rate

      

      
PSD935F2V-C-20U
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD935F2V-C-20UI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      
PSD935F2V-C-70B81
Configurable Memory System on a Chip for 8-Bit Microcontrollers

      

      

      

      


      


      

      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
PSD935G2-90U
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 TQFP-80 5V 4M 90N

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

      

      
PSD935G2V-90U
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD835G2V-90U

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

      

      
PSD954F2-90J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD854F2-90J

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

      

      
PSD954F2-90M
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD854F2-90M

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

      

      
PSD954F2V-90J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 2M 90ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

      

      
    
    
    
	
      	
    
    
     
     
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