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    參數(shù)資料
    型號: PSD935F2V-12B81
    廠商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲系統(tǒng)
    文件頁數(shù): 10/91頁
    文件大?。?/td> 488K
    代理商: PSD935F2V-12B81
    PSD935G2
    PSD9XX Family
    Pin*
    (TQFP
    Pin Name Pkg.)
    PA0-PA7
    Type
    I/O
    CMOS
    or Open
    Drain
    Description
    51-58
    Port A, PA0-7. This port is pin configurable and has multiple
    functions:
    1. MCU I/O — standard output or input port
    2. GPLD output.
    3. Input to the PLD.
    Port B, PB0-7. This port is pin configurable and has multiple
    functions:
    1. MCU I/O — standard output or input port.
    2. GPLD output.
    3. Input to the PLD.
    Port C, PC0-7. This port is pin configurable and has multiple
    functions:
    1. MCU I/O — standard output or input port.
    2. External chip select (ECS0-7) output.
    3. Input to the PLD.
    Port D pin PD0 can be configured as:
    1. ALE or AS input — latches addresses on ADIO0-15 pins
    2. AS input — latches addresses on ADIO0-15 pins on the
    rising edge.
    3. Input to the PLD.
    4. Transparent PLD input.
    Port D pin PD1 can be configured as:
    1. MCU I/O
    2. Input to the PLD.
    3. CLKIN clock input — clock input to the GPLD
    Micro
    Cells, the APD power down counter and GPLD
    AND Array.
    Port D pin PD2 can be configured as:
    1. MCU I/O
    2. Input to the PLD.
    3. CSI input — chip select input. When low, the CSI enables
    the internal PSD memories and I/O. When high, the
    internal memories are disabled to conserve power. CSI
    trailing edge can get the part out of power-down mode.
    PB0-PB7
    61-68
    I/O
    CMOS
    or Open
    Drain
    PC0-PC7 41-48
    I/O
    CMOS
    or Slew
    Rate
    PD0
    79
    I/O
    CMOS
    or Open
    Drain
    PD1
    80
    I/O
    CMOS
    or Open
    Drain
    PD2
    1
    I/O
    CMOS
    or Open
    Drain
    PD3
    2
    I/O
    Port D pin PD3 can be configured as:
    1. MCU I/O
    2. Input to the PLD.
    CMOS
    or Open
    Drain
    I/O
    CMOS
    or Open
    Drain
    PE0
    71
    Port E, PE0. This port is pin configurable and has multiple
    functions:
    1. MCU I/O — standard output or input port.
    2. Latched address output.
    3. TMS input for JTAG/ISP interface.
    Port E, PE1. This port is pin configurable and has multiple
    functions:
    1. MCU I/O — standard output or input port.
    2. Latched address output.
    3. TCK input for JTAG/ISP interface (Schmidt Trigger).
    Port E, PE2. This port is pin configurable and has multiple
    functions:
    1. MCU I/O — standard output or input port.
    2. Latched address output.
    3. TDI input for JTAG/ISP interface.
    PE1
    72
    I/O
    CMOS
    or Open
    Drain
    PE2
    73
    I/O
    CMOS
    or Open
    Drain
    Table 5.
    PSD935G2
    Pin
    Descriptions
    (cont.)
    9
    相關(guān)PDF資料
    PDF描述
    PSD935G2V-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G1-12MI 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: TSSOP 8 3.0x3.0x0.95 mm; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
    PSD935G1-12U 2.5V / 3.3V ECL Differential Receiver/Driver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
    PSD935G1-12UI 2.5V / 3.3V ECL Differential Receiver/Driver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
    PSD935G1-15B81 2.5V / 3.3V ECL Differential Receiver/Driver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
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