
P
P
4
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0
–
AD15
*
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
4 MBIT MAIN FLASH
MEMORY
8 SECTORS
VSTDBY
(PE6)
PA0
–
PA7
PROG.
PORT
PORT
F
PROG.
PORT
PORT
G
PROG.
PORT
PORT
E
PB0
–
PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PF0
–
PF7
PG0
–
PG7
PE0
–
PE7
PC0
–
PC7
PD0
–
PD3
ADDRESS/DATA/CONTROL BUS
66
66
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
64 KBIT BATTERY
BACKUP SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
GPLD OUTPUT
GPLD OUTPUT
GPLD OUTPUT
I/O PORT PLD INPUT
CSIOP
FLASH ISP PLD
(GPLD)
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
PAGE
REGISTER
EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
F
*
Additional address lines can be brought into PSD via Port A, B, C, D, or F.