參數(shù)資料
型號(hào)： PSD9135V12MT
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 1/110頁(yè)
文件大?。?/td> 1737K
代理商： PSD9135V12MT
1/110
PRELIMINARY DATA
June 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD813F2, PSD833F2
PSD834F2, PSD853F2, PSD854F2
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
FEATURES SUMMARY
FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
DUAL BANK FLASH MEMORIES
–
UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
–
UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
–
Concurrent operation: READ from one
memory while erasing and writing the
other
UP TO 256 Kbit BATTERY-BACKED SRAM
27 RECONFIGURABLE I/O PORTS
ENHANCED JTAG SERIAL PORT
PLD WITH MACROCELLS
–
Over 3000 Gates of PLD: CPLD and
DPLD
–
CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
–
DPLD - user defined internal chip select
decoding
27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions:
–
MCU I/Os
–
PLD I/Os
–
Latched MCU address output
–
Special function I/Os.
–
16 of the I/O ports may be configured as
open-drain outputs.
IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
–
Built-in JTAG compliant serial port allows
full-chip In-System Programmability
–
Efficient manufacturing allow easy
product testing and programming
–
Use low cost FlashLINK cable with PC
PAGE REGISTER
–
Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
PROGRAMMABLE POWER MANAGEMENT
■
■
■
■
■
■
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Figure 1. Packages
■
HIGH ENDURANCE:
–
100,000 Erase/WRITE Cycles of Flash
Memory
–
1,000 Erase/WRITE Cycles of PLD
–
15 Year Data Retention
5V±10% SINGLE SUPPLY VOLTAGE
STANDBY CURRENT AS LOW AS 50μA
■
■
PQFP52 (M)
PLCC52 (J)
TQFP64 (U)
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