參數(shù)資料
    

    


    


    
型號：
PSD854515JT

    

    
廠商：
意法半導體

    

    
英文描述：
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器

    

    
文件頁數(shù)：
67/110頁

    

    
文件大?。?/td>
1737K

    

    
代理商：
PSD854515JT


    

    

    

	
    
    
    

    
    
	
    67/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    RESET TIMING AND DEVICE STATUS AT RESET
    Power-Up Reset
    Upon Power-up, the PSD requires a Reset (RE-
    SET) pulse of duration t
    NLNH-PO
     after V
    CC
     is
    steady. During this period, the device loads inter-
    nal configurations, clears some of the registers
    and sets the Flash memory into Operating mode.
    After the rising edge of Reset (RESET), the PSD
    remains in the Reset mode for an additional peri-
    od, t
    OPR
    , before the first memory access is al-
    lowed.
    The Flash memory is reset to the READ Mode
    upon Power-up. Sector Select (FS0-FS7 and
    CSBOOT0-CSBOOT3) must all be Low, Write
    Strobe (WR, CNTL0) High, during Power On Re-
    set for maximum security of the data contents and
    to remove the possibility of a byte being written on
    the first edge of Write Strobe (WR, CNTL0). Any
    Flash memory WRITE cycle initiation is prevented
    automatically when V
    CC
     is below V
    LKO
    .
    Warm Reset
    Once the device is up and running, the device can
    be reset with a pulse of a much shorter duration,
    t
    NLNH
    .
    The same t
    OPR
     period is needed before the device
    is operational after warm reset. Figure 
    34
     shows
    the timing of the Power-up and warm reset.
    I/O Pin, Register and PLD Status at Reset
    Table 33., page 68
     shows the I/O pin, register and
    PLD status during Power On Reset, warm reset
    and Power-down mode. PLD outputs are always
    valid during warm reset, and they are valid in Pow-
    er On Reset once the internal PSD Configuration
    bits are loaded. This loading of PSD is completed
    typically long before the V
    CC
     ramps up to operat-
    ing level. Once the PLD is active, the state of the
    outputs are determined by the PSDabel equa-
    tions.
    Reset of Flash Memory Erase and Program 
    Cycles (on the PSD834Fx)
    A Reset (RESET) also resets the internal Flash
    memory state machine. During a Flash memory
    Program or Erase cycle, Reset (RESET) termi-
    nates the cycle and returns the Flash memory to
    the Read Mode within a period of t
    NLNH-A
    .
    Figure 34. Reset (RESET) Timing
    tNLNH-PO
    Power-On Reset
    tOPR
    AI02866b
    RESET
    tNLNH
    tNLNH-A
    Warm Reset
    tOPR
    V
    CC
    V
    CC
    (min)
    
    
    
    
    
    


    


    

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    PDF描述
    		

    
    

    
PSD854515MIT
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Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD854F2-15J
 制造商:STMicroelectronics 功能描述:4556DIE2HR - Trays

    

    
PSD854F2-70J
功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD854F2-70M
功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD854F2-90J
功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD854F2-90JI
功能描述:CPLD - 復雜可編程邏輯器件 5.0V 2M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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