參數(shù)資料
          

          


          


          
型號(hào)：
PSD8544V90JT

          

          
廠商：
意法半導(dǎo)體

          

          
英文描述：
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

          

          
中文描述：
Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器

          

          
文件頁數(shù)：
40/110頁

          

          
文件大小：
1737K

          

          
代理商：
PSD8544V90JT


          

          

          

	
          
    
    

    
          
	
          PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
          40/110
          Input Macrocells (IMC)
          The CPLD has 24 Input Macrocells (IMC), one for
          each pin on Ports A, B, and C. The architecture of
          the Input Macrocells (IMC) is shown in 
          Figure
          17., page 41
          . The Input Macrocells (IMC) are indi-
          vidually configurable, and can be used as a latch,
          register, or to pass incoming Port signals prior to
          driving them onto the PLD input bus. The outputs
          of the Input Macrocells (IMC) can be read by the
          MCU through the internal data bus.
          The enable for the latch and clock for the register
          are driven by a multiplexer whose inputs are a
          product term from the CPLD AND Array or the
          MCU Address Strobe (ALE/AS). Each product
          term output is used to latch or clock four Input
          Macrocells (IMC). Port inputs 3-0 can be con-
          trolled by one product term and 7-4 by another.
          Configurations for the Input Macrocells (IMC) are
          specified by equations written in PSDabel (see Ap-
          plication Note 
          AN1171
          ). Outputs of the Input Mac-
          rocells (IMC) can be read by the MCU via the IMC
          buffer. 
          See 
          the 
          section 
          PORTS, page 51
          .
          entitled 
          I/O
          Input Macrocells (IMC) can use Address Strobe
          (ALE/AS, PD0) to latch address bits higher than
          A15. Any latched addresses are routed to the
          PLDs as inputs.
          Input Macrocells (IMC) are particularly useful with
          handshaking communication applications where
          two processors pass data back and forth through
          a common mailbox. 
          Figure 18., page 42
           shows a
          typical configuration where the Master MCU writes
          to the Port A Data Out Register. This, in turn, can
          be read by the Slave MCU via the activation of the
          “Slave-Read” output enable product term.
          The Slave can also write to the Port A Input Mac-
          rocells (IMC) and the Master can then read the In-
          put Macrocells (IMC) directly.
          Note that the “Slave-Read” and “Slave-Wr” signals
          are product terms that are derived from the Slave
          MCU inputs Read Strobe (RD, CNTL1), Write
          Strobe (WR, CNTL0), and Slave_CS.
          
    
          
    
    
          


          


          

          相關(guān)PDF資料
          		

          PDF描述
          		

          
          

          
PSD814F4V-15
Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

          

          
PSD834F4V-15
Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

          

          
PSD854F4V-15
Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

          

          
PSD8134V20JIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

          

          
PSD9134V20JIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

          

          

          

          


          


          

          相關(guān)代理商/技術(shù)參數(shù)
          		

          參數(shù)描述
          		

          
          

          
PSD854F2-15J
 制造商:STMicroelectronics 功能描述:4556DIE2HR - Trays

          

          
PSD854F2-70J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

          

          
PSD854F2-70M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

          

          
PSD854F2-90J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

          

          
PSD854F2-90JI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

          

          
    
    
    
	
          	
    
    
     
     
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