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    參數(shù)資料
    型號: PSD853F3V-15
    廠商: 意法半導(dǎo)體
    英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
    文件頁數(shù): 59/110頁
    文件大?。?/td> 1737K
    代理商: PSD853F3V-15
    59/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    Port C – Functionality and Structure
    Port C can be configured to perform one or more
    of the following functions (see Figure
    29
    ):
    MCU I/O Mode
    CPLD Output – McellBC7-McellBC0 outputs
    can be connected to Port B or Port C.
    CPLD Input – via the Input Macrocells (IMC)
    Address In – Additional high address inputs
    using the Input Macrocells (IMC).
    In-System Programming (ISP) – JTAG port
    can be enabled for programming/erase of the
    PSD device. (See the section entitled
    PROGRAMMING IN-CIRCUIT USING THE
    JTAG SERIAL INTERFACE, page 69
    for
    more information on JTAG programming.)
    Open Drain – Port C pins can be configured in
    Open Drain Mode
    Battery Backup features – PC2 can be
    configured for a battery input supply, Voltage
    Stand-by (V
    STBY
    ).
    PC4 can be configured as a Battery-on Indicator
    (V
    BATON
    ), indicating when V
    CC
    is less than
    V
    BAT
    .
    Port C does not support Address Out mode, and
    therefore no Control Register is required.
    Pin PC7 may be configured as the DBE input in
    certain MCU bus interfaces.
    Figure 29. Port C Structure
    I
    DATA OUT
    REG.
    D
    Q
    D
    Q
    WR
    WR
    MCELLBC[7:0]
    ENABLE PRODUCT TERM (.OE)
    READ MUX
    P
    D
    B
    CPLD-INPUT
    DIR REG.
    INPUT
    MACROCELL
    ENABLE OUT
    SPECIAL FUNCTION1
    SPECIAL FUNCTION1
    CONFIGURATION
    BIT
    DATA IN
    OUTPUT
    SELECT
    OUTPUT
    MUX
    PORT C PIN
    DATA OUT
    AI02888B
    相關(guān)PDF資料
    PDF描述
    PSD853F3V-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD853F3V-70 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD853F3V-90 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD853F4-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD853F4-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD854F2-15J 制造商:STMicroelectronics 功能描述:4556DIE2HR - Trays
    PSD854F2-70J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD854F2-70M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD854F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD854F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100