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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD853590MIT

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器

    

    
文件頁(yè)數(shù)：
63/110頁(yè)

    

    
文件大?。?/td>
1737K

    

    
代理商：
PSD853590MIT


    

    

    

	
    
    
    

    
    
	
    63/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    Automatic Power-down (APD) Unit and Power-down Mode
    The APD Unit, shown in Figure 
    32
    , puts the PSD
    into Power-down mode by monitoring the activity
    of Address Strobe (ALE/AS, PD0). If the APD Unit
    is enabled, as soon as activity on Address Strobe
    (ALE/AS, PD0) stops, a four bit counter starts
    counting. If Address Strobe (ALE/AS, PD0) re-
    mains inactive for fifteen clock periods of CLKIN
    (PD1), Power-down (PDN) goes High, and the
    PSD enters Power-down mode, as discussed
    next.
    Power-down Mode.
     By default, if you enable the
    APD Unit, Power-down mode is automatically en-
    abled. The device enters Power-down mode if Ad-
    dress Strobe (ALE/AS, PD0) remains inactive for
    fifteen periods of CLKIN (PD1).
    The following should be kept in mind when the
    PSD is in Power-down mode:
    –
    If Address Strobe (ALE/AS, PD0) starts 
    pulsing again, the PSD returns to normal 
    Operating mode. The PSD also returns to 
    normal Operating mode if either PSD Chip 
    Select Input (CSI, PD2) is Low or the Reset 
    (RESET) input is High.
    –
    The MCU address/data bus is blocked from all 
    memory and PLDs.
    –
    Various signals can be blocked (prior to 
    Power-down mode) from entering the PLDs by 
    setting the appropriate bits in the PMMR 
    registers. The blocked signals include MCU 
    control signals and the common CLKIN (PD1). 
    Note that blocking CLKIN (PD1) from the 
    PLDs does not block CLKIN (PD1) from the 
    APD Unit.
    All PSD memories enter Standby mode and 
    are drawing standby current. However, the 
    PLD and I/O ports blocks do 
    not
    go into 
    Standby Mode because you don’t want to 
    have to wait for the logic and I/O to “wake-up” 
    before their outputs can change. See Table 
    28
    for Power-down mode effects on PSD ports.
    Typical standby current is of the order of 
    microamperes. These standby current values 
    assume that there are no transitions on any 
    PLD input.
    –
    –
    Table 28. Power-down Mode’s Effect on Ports
    Figure 32. APD Unit
    Table 29. PSD Timing and Stand-by Current during Power-down Mode
    Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
    2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’
    Port Function 
    Pin Level
    MCU I/O 
    No Change
    PLD Out 
    No Change
    Address Out 
    Undefined
    Data Port 
    Tri-State
    Peripheral I/O 
    Tri-State
    Mode
    PLD Propagation 
    Delay
    Memory 
    Access Time
    Access Recovery Time 
    to Normal Access
    Typical Stand-by Current
    5V V
    CC
    3V V
    CC
    Power-down
    Normal t
    PD
     (Note 
    1
    )
    No Access
    t
    LVDV
    75μA (Note 
    2
    )
    25μA (Note 
    2
    )
    APD EN
    PMMR0 BIT 1=1
    ALE
    RESET
    CSI
    CLKIN
    TRANSITION
    DETECTION
    EDGE
    DETECT
    APD
    COUNTER
    POWER DOWN
    (PDN) 
    SELECT
    DISABLE BUS
    INTERFACE
    EEPROM SELECT
    FLASH SELECT
    SRAM SELECT
    PD
    CLR
    PD
    DISABLE
    FLASH/EEPROM/SRAM
    PLD
    AI02891
    
    
    
    
    
    


    


    

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    PDF描述
    		

    
    

    
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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD853F2-70J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 70ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD853F2-70M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90JI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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