<menuitem id="fedsm"></menuitem>
  • <li id="fedsm"></li>
    <form id="fedsm"><meter id="fedsm"><sub id="fedsm"></sub></meter></form>
  • <dfn id="fedsm"><pre id="fedsm"><dfn id="fedsm"></dfn></pre></dfn><dfn id="fedsm"><pre id="fedsm"></pre></dfn>
    參數(shù)資料
    型號(hào): PSD835F2-B-90B81
    廠商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
    文件頁(yè)數(shù): 15/110頁(yè)
    文件大?。?/td> 570K
    代理商: PSD835F2-B-90B81
    PSD8XX Family
    PSD835G2
    14
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    *
    *
    *
    *
    *
    *
    JTAG_Enable
    JTAG Enable Register
    Bit definitions:
    JTAG_Enable
    1 = JTAG Port is Enabled.
    0 = JTAG Port is Disabled.
    8.0
    Register Bit
    Definition
    (cont.)
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Pgr7
    Pgr6
    Pgr5
    Pgr4
    Pgr3
    Pgr2
    Pgr1
    Pgr0
    Page Register
    Bit definitions:
    Configure Page input to PLD. Default Pgr[7:0] = 00.
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    *
    PLD
    PLD
    array-clk
    PLD
    Turbo
    *
    APD
    enable
    *
    Mcells clk
    PMMR0 Register
    Bit definitions: (default is 0)
    Bit 1 0 = Automatic Power Down (APD) is disabled.
    1 = Automatic Power Down (APD) is enabled.
    Bit 3 0 = PLD Turbo is on.
    1 = PLD Turbo is off, saving power.
    Bit 4 0 = CLKIN input to the PLD AND array is connected.
    Every CLKIN change will power up the ZPLD when Turbo bit is off.
    1 = CLKIN input to PLD AND array is disconnected, saving power.
    Bit 5 0 = CLKIN input to the PLD Micro
    Cells is connected.
    1 = CLKIN input to the PLD Micro
    Cells is disconnected, saving power.
    *
    Not used bit should be set to zero.
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    PLD
    PLD
    PLD
    PLD
    PLD
    *
    *
    array WRh
    array Ale
    array Cntl2 array Cntl1 array Cntl0
    PMMR1 Register
    Bit definitions (default is 0):
    Bit 0 0 = Address A[7:0] are connected into the PLD array.
    1 = Address A[7:0] are blocked from the PLD array, saving power.
    Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4.
    Bit 2 0 = Cntl0 input to the PLD AND array is connected.
    1 = Cntl0 input to the PLD AND array is disconnected, saving power.
    Bit 3 0 = Cntl1 input to the PLD AND array is connected.
    1 = Cntl1 input to the PLD AND array is disconnected, saving power.
    Bit 4 0 = Cntl2 input to the PLD AND array is connected.
    1 = Cntl2 input to the PLD AND array is disconnected, saving power.
    Bit 5 0 = Ale input to the PLD AND array is connected.
    1 = Ale input to the PLD AND array is disconnected, saving power.
    Bit 6 0 = WRh/DBE input to the PLD AND array is connected.
    1 = WRh/DBE input to the PLD AND array is disconnected, saving power.
    *
    Not used bit should be set to zero.
    相關(guān)PDF資料
    PDF描述
    PSD835F2-B-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2-B-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2-C-20B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2-C-20B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD835F2-C-20J Configurable Memory System on a Chip for 8-Bit Microcontrollers
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD835G2-70U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
    PSD835G2-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
    PSD835G2-90UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
    PSD835G2V-12UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
    PSD835G2V-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray