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參數(shù)資料
| 型號： | PSD835F1V-B-70M |
| 廠商： | 意法半導體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲系統(tǒng) |
| 文件頁數(shù)： | 42/110頁 |
| 文件大?。?/td> | 570K |
| 代理商： | PSD835F1V-B-70M |
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PSD835G2
PSD8XX Family
41
9.2.2.6 Input Micro
Cells (IMCs)
The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC
is shown in Figure 14. The IMCs are individually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The
outputs of the IMCs can be read by the microcontroller through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each
product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by
one product term and 7-4 by another.
Configurations for the IMCs are specified by PSDsoft. Outputs of the IMCs can be read by
the MCU via the IMC buffer. See the I/O Port section on how to read the IMCs.
IMCs can use the address strobe to latch address bits higher than A15. Any latched
addresses are routed to the PLDs as inputs.
IMCs are particularly useful with handshaking communication applications where two
processors pass data back and forth through a common mailbox. Figure 15 shows a typical
configuration where the Master MCU writes to the Port A Data Out Register. This, in turn,
can be read by the Slave MCU via the activation of the
“
Slave-Read
”
output enable product
term. The Slave can also write to the Port A IMCs and the Master can then read the IMCs
directly. Note that the
“
Slave-Read
”
and
“
Slave-Wr
”
signals are product terms that are
derived from the Slave MCU inputs RD, WR, and Slave_CS.
The
PSD835G2
Functional
Blocks
(cont.)
OUTPUT
MICRO
CELLS A
AND
MICRO
CELL B
PT
PT
FEEDBACK
A
P
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH
INPUT MICRO
CELL
ENABLE (.OE)
D FF
INPUT MICRO
CELL_ RD
Figure 14. Input Micro
Cell
相關PDF資料 |
PDF描述 |
|---|---|
| PSD835F1V-B-70MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-B-70U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-B-70UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-B-90B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835F1V-B-90B81I | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD835G2-70U | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90U | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90UI | 功能描述:靜態(tài)隨機存取存儲器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-12UI | 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-90U | 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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