參數(shù)資料
型號(hào)： PSD713S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入）
文件頁(yè)數(shù)： 12/104頁(yè)
文件大?。?/td> 515K
代理商： PSD713S5
PSD7XX Family
13-12
PSD7XX devices consist of several major functional blocks. Figure 1 shows the architecture
of the PSD7XX family. The functions of each block are described briefly in the following
sections. Many of the blocks perform multiple functions, and are user configurable.
PLDs
The device contains four PLD blocks each optimized for a different function as shown in
Table 6. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance and ease of design entry.
The Decode PLD (DPLD) is used to decode and generate chip selects for the PSD7XX
internal memory, registers and peripheral mode. The External Chip Select PLD (ECSPLD) is
optimized to generate chip selects for devices external to the PSD7XX. The General
Purpose PLD (GPLD) can implement user defined logic functions. The DPLD and ECSPLD
have combinatorial outputs while the GPLD has 12 Output Micro
Cells. The PSD7XX also
has 24 Input Micro
Cells that can be configured as inputs to the PLD. The PLDs receive
their inputs from the PLD Input bus and are differentiated by their output destinations,
number of product terms, and Micro
Cells.
The Peripheral PLD (PPLD) is dedicated to generate control signals for the WatchDog timer.
PSD7XX
Architectural
Overview
Name
Abbreviation
Inputs
Outputs
Product Terms
Decode PLD
DPLD
46
12
13
External Chip Select PLD
ECSPLD
24
7
7
General PLD
GPLD
66
12
110
Peripheral PLD
PPLD
66
2
2
Table 6.
I/O Ports
The PSD7XX has 27 I/O pins divided among four ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B, C and D can be configured as standard
MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed
address/data busses.
Ports A and B can also be configured as a data port for microcontrollers with a
non-multiplexed bus. In these modes, Port A is connected to D0–7 and Port B to D8–15.
Supervisory Functions
The PSD7XX provides all the supervisory functions required for an embedded system.
A voltage comparator monitors the system power supply and generates a reset if V
CC
drops
below internal or external reference voltages (hysterisis included). The polarity and duration
of the reset output signal is programmable.
A noise filter for the reset input is provided to debounce the source (pushbutton or other).
The internal PSD7XX SRAM is automatically switched to standby voltage if V
CC
drops
below the standby voltage value. When switchover occurs, the internal SRAM is write
protected and a single user defined chip select output immediately goes inactive. This
special chip select supports the use of an additional external battery backup SRAM (to
ensure low power consumption during a fault) or provides protection against inadvertent
writes to external FLASH or EEPROM.
A WatchDog timer is provided to monitor software integrity. Normal program flow will
continually reset the WatchDog timer. However, if program flow malfunctions and hangs up,
the timer will timeout and reset the system. This 9-bit WatchDog timer is programmable and
can supply its own independent clock source.
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