參數(shù)資料
型號(hào): PSD4256G6V-10UIT
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals for 16-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的周邊的16位微控制器
文件頁(yè)數(shù): 37/100頁(yè)
文件大?。?/td> 759K
代理商: PSD4256G6V-10UIT
37/100
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS15,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note AN1154
Table 22, page 22 and Figure 11 show the Page
Register. The eight flip-flops in the register are
connected to the internal data bus (D0-D7). The
MCU can write to or read from the Page Register.
The Page Register can be accessed at address lo-
cation CSIOP + E0h.
Figure 11. Page Register
MEMORY ID REGISTERS
The 8-bit “Read only” Memory Status Registers
are included in the CSIOP space. The user can
determine the memory configuration of the PSD
device by reading the Memory ID0 and Memory
ID1 registers. The content of the registers is de-
fined as shown in Table 26, page 24 and Table 27,
page 24.
RESET
D0 - D7
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI02871B
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