- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368213 > PSD4235G3-A-20M (意法半導(dǎo)體) CAP 0.68UF 35V 10% TANT SMD-3216-18 TR-13-PL GOLD PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD4235G3-A-20M |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 0.68UF 35V 10% TANT SMD-3216-18 TR-13-PL GOLD |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁數(shù)： | 63/93頁 |
| 文件大小： | 503K |
| 代理商： | PSD4235G3-A-20M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁當(dāng)前第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
PSD4000 Series
Preliminary Information
60
The
PSD4000
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
9.5.3.1 Power On Reset
Upon power up the PSD4000 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
V
CC
is steady. During this time period the device loads internal configurations, clears
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD4000 remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD4000 Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of data being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V
CC
is below VLKO.
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 26 shows the timing of the power on and warm reset.
OPERATING LEVEL
POWER ON RESET
V
CC
RESET
tNLNH
–
PO
tOPR
tNLNH-A
tNLNH
tOPR
WARM
RESET
Figure 26. Power On and Warm Reset Timing
9.5.3.3
I/OPin, Register and PLD Status at Reset
Table 28 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V
CC
ramps up to operating level. Once the PLD
is active, the state of the outputs are determined by the equations specified in PSDsoft.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4235G3-A-20MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G3-A-20U | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G3-A-20UI | CAP 0.68UF 35V 10% TANT SMD-3216-18 TR-13-PL SN100% |
| PSD4235G3-A-70B81 | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G3-A-70B81I | CAP 0.68UF 20V 20% TANT SMD-3216-18 TR-13-PL GOLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45_11 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45A-05 | 功能描述:線性和開關(guān)式電源 30W 5Vout 6A Input 9.2-18VDC RoHS:否 制造商:TDK-Lambda 產(chǎn)品:Switching Supplies 開放式框架/封閉式:Enclosed 輸出功率額定值:800 W 輸入電壓:85 VAC to 265 VAC 輸出端數(shù)量:1 輸出電壓（通道 1）:20 V 輸出電流（通道 1）:40 A 商用/醫(yī)用: 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:Rack 長(zhǎng)度: 寬度: 高度: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。