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    參數(shù)資料
    型號: PSD4235G2V-B-70MI
    廠商: 意法半導體
    英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述: Flash在系統(tǒng)可編程外設的16位微控制器
    文件頁數(shù): 6/93頁
    文件大?。?/td> 503K
    代理商: PSD4235G2V-B-70MI
    Preliminary Information
    PSD4000 Series
    11
    Table 6 shows the offset addresses to the PSD4000 registers relative to the CSIOP base
    address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
    internal PSD4000 registers. Table 6 provides brief descriptions of the registers in CSIOP
    space. For a more detailed description, refer to section 9.
    7.0 PSD4000
    Register
    Description and
    Address Offset
    Register Name
    Port A
    Port B
    Port C
    Port D
    Port E
    Port F
    Port G
    Other*
    Description
    Data In
    00
    01
    10
    11
    30
    40
    41
    Reads Port pin as input,
    MCU I/O input mode
    Control
    32
    42
    43
    Selects mode between
    MCU I/O or Address Out
    Stores data for output
    Data Out
    04
    05
    14
    15
    34
    44
    45
    to Port pins, MCU I/O
    output mode
    Direction
    06
    07
    16
    17
    36
    46
    47
    Configures Port pin as
    input or output
    Configures Port pins as
    either CMOS or Open
    Drive Select
    08
    09
    18
    19
    38
    48
    49
    Drain on some pins, while
    selecting high slew rate
    on other pins.
    Flash Protection
    C0
    Read only – Flash Sector
    Protection
    Flash Boot
    Read only – PSD Security
    Protection
    C2
    and Flash Boot Sector
    Protection
    PMMR0
    B0
    Power Management
    Register 0
    PMMR2
    B4
    Power Management
    Register 2
    Page
    E0
    Page Register
    Places PSD memory
    VM
    E2
    areas in Program and/or
    Data space on an
    individual basis.
    Memory_ID0
    F0
    Read only – Flash and
    SRAM size
    Memory_ID1
    F1
    Read only – Boot type
    and size
    Table 6. Register Address Offset
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