參數(shù)資料
型號(hào): PSD4235G2V-70UI
廠商: 意法半導(dǎo)體
英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù): 76/89頁(yè)
文件大?。?/td> 702K
代理商: PSD4235G2V-70UI
PSD4235G2V
76/89
Table 65. Read Timing
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
Symbol
Parameter
Conditions
-90
-12
Turbo
Off
Unit
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
22
24
ns
t
AVLX
Address Setup Time
(Note
3
)
7
9
ns
t
LXAX
Address Hold Time
(Note
3
)
8
10
ns
t
AVQV
Address Valid to Data Valid
(Note
3
)
90
120
+ 20
ns
t
SLQV
CS Valid to Data Valid
90
120
ns
t
RLQV
RD to Data Valid 8-Bit Bus
(Note
5
)
35
35
ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
(Note
2
)
45
48
ns
t
RHQX
RD Data Hold Time
(Note
1
)
0
0
ns
t
RLRH
RD Pulse Width
36
40
ns
t
RHQZ
RD to Data High-Z
(Note
1
)
38
40
ns
t
EHEL
E Pulse Width
38
42
ns
t
THEH
R/W Setup Time to Enable
10
16
ns
t
ELTL
R/W Hold Time After Enable
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note
4
)
30
35
ns
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