• <button id="hktir"></button>
      <samp id="hktir"><small id="hktir"><optgroup id="hktir"></optgroup></small></samp>
      <rp id="hktir"><tbody id="hktir"></tbody></rp>
    • <rp id="hktir"></rp>
      <i id="hktir"><form id="hktir"></form></i>
      參數(shù)資料
      型號(hào)： PSD4235G2V-70U
      廠商： 意法半導(dǎo)體
      英文描述： Tantalum Electrolytic Capacitor; Capacitance:68uF; Capacitance Tolerance:+/- 20 %; Working Voltage, DC:6.3V; Package/Case:3528-21; Terminal Type:PCB SMT; ESR:0.004ohm; Operating Temp. Max:105 C; Operating Temp. Min:-55 C
      中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
      文件頁(yè)數(shù)： 21/89頁(yè)
      文件大?。?/td> 702K
      代理商： PSD4235G2V-70U
      21/89
      PSD4235G2V
      Primary Flash Memory and Secondary Flash
      memory Description.
      The primary Flash memo-
      ry is divided evenly into 8 sectors. The secondary
      Flash memory is divided evenly into 4 sectors.
      Each sector of either memory block can be sepa-
      rately protected from Program and Erase cycles.
      Flash memory may be erased on a sector-by-sec-
      tor basis, and programmed word-by-word. Flash
      sector erasure may be suspended while data is
      read from other sectors of the block and then re-
      sumed after reading.
      During a Program or Erase cycle in Flash memory,
      the status can be output on the Ready/Busy pin
      (PE4). This pin is set up using PSDsoft Express.
      Memory Block Select Signals.
      The DPLD gen-
      erates the Select signals for all the internal memo-
      ry blocks (see the section entitled “PLDs”, on page
      31). Each of the sectors of the primary Flash mem-
      ory has a Select signal (FS0-FS7) which can con-
      tain up to three product terms. Each of the sectors
      of the secondary Flash memory has a Select sig-
      nal (CSBOOT0-CSBOOT3) which can contain up
      to three product terms. Having three product terms
      for each Select signal allows a given sector to be
      mapped in different areas of system memory.
      When using a MCU with separate Program and
      Data space (80C51XA), these flexible Select sig-
      nals allow dynamic re-mapping of sectors from
      one memory space to the other before and after
      IAP. The SRAM block has a single Select signal
      (RS0).
      Ready/Busy (PE4).
      This signal can be used to
      output the Ready/Busy status of the PSD. The out-
      put is a 0 (Busy) when a Flash memory block is be-
      ing written to,
      or
      when a Flash memory block is
      being erased. The output is a 1 (Ready) when no
      Write or Erase cycle is in progress.
      Memory Operation.
      The primary Flash memory
      and secondary Flash memory are addressed
      through the MCU Bus Interface. The MCU can ac-
      cess these memories in one of two ways:
      I
      The MCU can execute a typical bus Write or
      Read
      operation
      just as it would if accessing a
      RAM or ROM device using standard bus cycles.
      I
      The MCU can execute a specific instruction that
      consists of several Write and Read operations.
      This involves writing specific data patterns to
      special addresses within the Flash memory to
      invoke an embedded algorithm. These
      instructions are summarized in Table 29.
      Typically, the MCU can read Flash memory using
      Read operations, just as it would read a ROM de-
      vice. However, Flash memory can only be erased
      and programmed using specific instructions. For
      example, the MCU cannot write a single byte di-
      rectly to Flash memory as one would write a byte
      to RAM. To program a word into Flash memory,
      the MCU must execute a Program instruction, then
      test the status of the Programming event. This sta-
      tus test is achieved by a Read operation or polling
      Ready/Busy (PE4).
      Flash memory can also be read by using special
      instructions to retrieve particular Flash device in-
      formation (sector protect status and ID).
      相關(guān)PDF資料
      PDF描述
      PSD4235G2V-70UI Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4235G2V-70UT Flash In-System Programmable ISP Peripherals For 16-bit MCUs 3.3V Supply
      PSD4235G2V-15B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4235G2V-15B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4235G2V-15J Fail-Safe Floating Electrode MLCC / FE-CAP / X7R Dielectric; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R; Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Tin (Sn) Plated Nickel Barrier; Body Dimensions: 0.126&quot; x 0.063&quot;; Container: Bulk; Features: Fail-Safe Floating Electrode; Unmarked
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
      PSD4256G6V-10UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
      PSD4-36 制造商:Tamura Corporation of America 功能描述:
      PSD-45 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply
      PSD-45_11 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply
      發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

      采購(gòu)需求

      (若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

      發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

      發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

      *型號(hào) *數(shù)量 廠商 批號(hào) 封裝
      添加更多采購(gòu)

      我的聯(lián)系方式

      *
      *
      *