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參數(shù)資料
| 型號： | PSD4235G2-A-15U |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 42/104頁 |
| 文件大?。?/td> | 1114K |
| 代理商： | PSD4235G2-A-15U |
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Obsolete
Product(s)
- Obsolete
Product(s)
Memory blocks delailed operation
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
The Reset instruction will reset the Flash to normal Read mode immediately. However, if
there is an error condition (DQ5 (DQ13) goes high), the Flash memory will return to the
Read mode in 25 s after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk Erase
cycle. The Reset instruction will abort the on going sector erase cycle and return the Flash
memory to normal Read mode in 25 s.
7.1.11
Reset (RESET) pin input
The reset pulse input from the pin will abort any operation in progress and reset the Flash
memory to Read mode. When the reset occurs during a programming or erase cycle, the
Flash memory will take up to 25 s to return to Read mode. It is recommended that the reset
pulse (except Power-on reset, see Section 7.1.10: Reset ) be at least 25 Seconds such
that the Flash memory will always be ready for the MCU to fetch the boot code after reset is
over.
7.2
SRAM
The SRAM is enabled when RS0—the SRAM chip select output from the DPLD—is high.
RS0 can contain up to three product terms, allowing flexible memory mapping.
The Chip Select signal (RS0) for the SRAM is configured using PSDsoft.
7.3
Memory Select signals
The primary Flash (FSi), secondary Flash (CSBOOTi), and SRAM (RS0) memory select
signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules
apply to the equations for the internal chip select signals:
●
Primary Flash memory and secondary Flash memory sector select signals must not be
larger than the physical sector size.
●
Any primary Flash memory sector must not be mapped in the same memory space as
another primary Flash sector.
●
A secondary Flash memory sector must not be mapped in the same memory space as
another Flash Boot sector.
●
SRAM and I/O spaces must not overlap.
●
A secondary Flash memory sector may overlap a primary Flash memory sector. In
case of overlap, priority will be given to the Flash Boot sector.
●
SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority
will be given to the SRAM, and I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) will automatically address Boot memory segment 0. Any address
greater than 9FFFh will access the Flash memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this
相關PDF資料 |
PDF描述 |
|---|---|
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| PSD813F2A-15JI | 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD834F2VA-15MI | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| PSD854F2A-90MT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2V-12UI | 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4256G6V-10UI | 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
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