- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄368153 > PSD4135G2V 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; IRHMS57163SE JANS Certified Part Number PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD4135G2V |
| 英文描述： | 130V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; IRHMS57163SE JANS Certified Part Number |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁(yè)數(shù)： | 32/93頁(yè) |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135G2V |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
Preliminary Information
PSD4000 Series
29
RESET
DATA BUS
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
GPLD
INTERNAL
SELECTS
AND LOGIC
FLASH
PLD
PGR4
PGR5
PGR6
PGR7
Figure 8. Page Register
The
PSD4000
Functional
Blocks
(cont.)
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller.
The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and
can be included in the Flash Memory, secondary Flash memory, and SRAM chip select
equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the PLD for general logic. See Application
Notes.
Figure 8 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus. The microcontroller can write to or read from the Page Register. The
Page Register can be accessed at address location CSIOP + E0h.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4135F1-70B81 | LCD Display Panel; No. of Digits/Alpha:64; Display Technology:LCD; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| PSD4135G1-70B81 | LCD Character display; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| PSD4135F2-70B81 | LCD Character display; No. of Digits/Alpha:48; Display Technology:LCD; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| PSD4135G2-70B81 | LCD Character display; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| PSD4135F1-B-70B81 | LCD Display Panel; Signal Input Type:TFT Analog RGB, NTSC, PAL; Display Technology:LCD; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:12V RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G2V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2V-12J | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2V-12JI | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2V-12M | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。