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參數(shù)資料
| 型號： | PSD4135G1V-90MI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁數(shù)： | 57/93頁 |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135G1V-90MI |
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PSD4000 Series
Preliminary Information
54
The
PSD4000
Functional
Blocks
(cont.)
I
DATA OUT
REG.
D
Q
D
G
Q
D
Q
D
Q
WR
WR
WR
ADDRESS
ALE
READ MUX
P
D
B
CONTROL REG.
DIR REG.
PLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
CONFIGURATION
BIT
Figure 23. Ports E, F and G Structure
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
PLD Input
–
as direct input ot the PLD array.
J
Address In
–
additional high address inputs. Direct input to the PLD array.
J
Latched Address Out
–
Provide latched address out per Table 29.
J
Slew Rate
–
pins can be set up for fast slew rate.
J
Data Port
–
connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
J
MCU Reset Mode
–
for 16-bit Motorola 683XX and HC16 microcontrollers.
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
Latched Address Out
–
provide latched address out per Table 29.
J
Open Drain
–
pins can be configured in Open Drain Mode
J
Data Port
–
connected to D[15:8] when Port G is configured as Data Port for a
non-multiplexed bus.
J
MCU Reset Mode
–
for 16-bit Motorola 683XX and HC16 microcontrollers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4135G1V-90U | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.252"; Container: Bulk; Features: Unmarked |
| PSD4135G1V-90UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81I | CAP 0.01UF 50V 5% NP0(C0G) SMD-1825 TR-7-PL SN-NIBAR |
| PSD4135G1V-A-12J | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.252"; Container: Bulk; Features: Unmarked |
| PSD4135G1V-A-12JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G1V-90U | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-90UI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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