參數(shù)資料
        型號: PSD4135G1-C-12JI
        廠商: 意法半導(dǎo)體
        英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
        中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
        文件頁數(shù): 73/93頁
        文件大小: 503K
        代理商: PSD4135G1-C-12JI
        PSD4000 Series
        Preliminary Information
        70
        -70
        -90
        Symbol
        Parameter
        Conditions
        Min
        Max
        Min
        Max
        Unit
        t
        LVLX
        t
        AVLX
        t
        LXAX
        ALE or AS Pulse Width
        15
        20
        Address Setup Time
        (Note 1)
        4
        6
        ns
        Address Hold Time
        (Note 1)
        7
        8
        ns
        t
        AVWL
        Address Valid to Leading
        Edge of WR
        (Notes 1 and 3)
        8
        15
        ns
        t
        SLWL
        t
        DVWH
        t
        WHDX
        t
        WLWH
        CS Valid to Leading Edge of WR
        (Note 3)
        12
        15
        ns
        WR Data Setup Time
        (Note 3)
        25
        35
        ns
        WR Data Hold Time
        (Note 3)
        4
        5
        ns
        WR Pulse Width
        (Note 3)
        28
        35
        ns
        t
        WHAX1
        Trailing Edge of WR to Address
        Invalid
        (Note 3)
        6
        8
        ns
        t
        WHAX2
        Trailing Edge of WR to DPLD
        Address Input Invalid
        (Note 3 and 4)
        0
        0
        ns
        t
        WHPV
        Trailing Edge of WR to Port Output
        Valid Using I/O Port Data Register
        (Note 3)
        27
        30
        ns
        t
        AVPV
        Address Input Valid to Address
        Output Delay
        (Note 2)
        20
        25
        ns
        Write Timing
        (5 V ± 10% Versions)
        NOTES:
        1.
        Any input used to select an internal PSD4000 function.
        In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
        WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
        t
        WHAX2
        is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
        2.
        3.
        4.
        Microcontroller Interface – PSD4000 AC/DC Parameters
        (5V ±10% Versions)
        -70
        -90
        Slew
        Rate
        (Note 1)
        TURBO
        OFF
        Symbol
        Parameter
        Conditions
        Min
        Max
        Min
        Max
        Unit
        t
        PD
        PLD Input Pin/Feedback to
        PLD Combinatorial Output
        20
        25
        Add 12
        Sub 2
        ns
        t
        ARD
        PLD Array Delay
        11
        16
        ns
        PLD Combinatorial Timing
        (5 V ± 10%)
        NOTE:
        1. Fast Slew Rate output available on Port C and F.
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