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| 型號(hào)： | PSD4135G1-B-70B81 |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | LCD Display Panel; Signal Input Type:TFT Analog RGB, NTSC, PAL; Display Technology:LCD; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:12V RoHS Compliant: No |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁(yè)數(shù)： | 54/93頁(yè) |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135G1-B-70B81 |
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Preliminary Information
PSD4000 Series
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port C
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port D
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port E
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port F
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port G
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Table 22. Drive Register Pin Assignment
The
PSD4000
Functional
Blocks
(cont.)
9.4.3.3 Drive Select Register
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should
be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register
is set to a
‘
1
’
. The default pin drive is CMOS.
Aside:
the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates in a high slew rate when the corresponding bit in the Drive Register is set to
‘
1
’
.
The default rate is slow slew.
Table 22 shows the Drive Register for Ports A, B, C, D, E, F and G. It summarizes which
pins can be configured as Open Drain outputs and which pins the slew rate can be set for.
51
9.4.4 Port Data Registers
The Port Data Registers, shown in Table 23, are used by the microcontroller to write data
to or read data from the ports. Table 23 shows the register name, the ports having each
register type, and microcontroller access for each register type. The registers are
described below.
9.4.4.1 Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input
is read through the Data In buffer.
9.4.4.2 Data Out Register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable
product term is set to
“
1
”
. The contents of the register can also be read back by the
microcontroller.
Table 27. Port Data Registers
Register Name
Port
MCU Access
Data In
A,B,C,D,E,F,G
Read
–
input on pin
Data Out
A,B,C,D,E,F,G
Write/Read
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PDF描述 |
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| PSD4135G2-B-70B81 | LCD Display Panel; Signal Input Type:NTSC Composite, RGB, VGA; Display Technology:LCD; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:12V RoHS Compliant: No |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G1-B-70B81I | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1-B-70J | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1-B-70JI | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1-B-70M | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1-B-70MI | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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