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      參數資料
      型號: PSD4135F2-C-15JI
      廠商: 意法半導體
      英文描述: Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.012uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126&quot; x 0.098&quot;; Container: Bulk; Features: Unmarked
      中文描述: Flash在系統(tǒng)可編程外設的16位微控制器
      文件頁數: 9/93頁
      文件大小: 503K
      代理商: PSD4135F2-C-15JI
      PSD4000
      Architectural
      Overview
      (cont.)
      4.5 ISP via JTAG Port
      In-System Programming can be performed through the JTAG pins on Port E. This serial
      interface allows complete programming of the entire PSD4000 device. A blank device can
      be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
      be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin
      assignments.
      4.6 In-System Programming (ISP)
      Using the JTAG signals on Port E, the entire PSD4000 (memory, logic, configuration)
      device can be programmed or erased without the use of the microcontroller.
      Port E Pins
      PE0
      PE1
      PE2
      PE3
      PE4
      PE5
      JTAG Signal
      TMS
      TCK
      TDI
      TDO
      TSTAT
      TERR
      Table 3. JTAG Signals on Port E
      PSD4000 Series
      Preliminary Information
      6
      4.7 In-Application re-Programming (IAP)
      The main Flash memory can also be programmed in-system by the microcontroller
      executing the programming algorithms out of the secondary Flash memory, or SRAM.
      Since this is a sizable separate block, the application can also continue to operate. The
      secondary Flash boot memory can be programmed the same way by executing out of the
      main Flash memory. Table 4 indicates which programming methods can program different
      functional blocks of the PSD4000.
      Device
      Programmer
      Yes
      Yes
      Yes
      Yes
      Functional Block
      Main Flash memory
      Flash Boot memory
      PLD Array (DPLD and GPLD)
      PSD Configuration
      JTAG-ISP
      Yes
      Yes
      Yes
      Yes
      IAP
      Yes
      Yes
      No
      No
      Table 4. Methods of Programming Different Functional Blocks of the PSD4000
      4.8 Page Register
      The eight-bit Page Register expands the address range of the microcontroller by up to
      256 times.The paged address can be used as part of the address space to access
      external memory and peripherals or internal memory and I/O. The Page Register can also
      be used to change the address mapping of blocks of Flash memory into different memory
      spaces for IAP.
      4.9 Power Management Unit
      The Power Management Unit (PMU) in the PSD4000 gives the user control of the
      power consumption on selected functional blocks based on system requirements. The
      PMU includes an Automatic Power Down unit (APD) that will turn off device functions due
      to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce
      power consumption.
      The PSD4000 also has some bits that are configured at run-time by the MCU to reduce
      power consumption of the GPLD. The turbo bit in the PMMR0 register can be turned off
      and the GPLD will latch its outputs and go to standby until the next transition on its inputs.
      Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
      entering the GPLD to reduce power consumption. See section 9.5.
      相關PDF資料
      PDF描述
      PSD4135F2-C-15M Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-15MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-15U Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-15UI Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-20B81 Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.012uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126&quot; x 0.098&quot;; Container: Bulk; Features: Unmarked
      相關代理商/技術參數
      參數描述
      PSD4135F2-C-15M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-15MI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-15U 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-15UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
      PSD4135F2-C-20B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs