參數(shù)資料
型號(hào)： PSD412A2
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入）
文件頁數(shù)： 12/97頁
文件大?。?/td> 309K
代理商： PSD412A2
PSD4XX Famly
4-12
The GPLD
The structure of the General Purpose PLD consists of a programmable AND ARRAY
and 2 sets of I/O Macrocells. The ARRAY has 37 input signals, same as the DPLD.
From these inputs, “ANDed” functions are generated as product term inputs to the
macrocells. The I/O Macrocell sets are named after the I/O Ports they are linked to,
e.g., the macrocells connected to Port B are named PB Macrocells. The PB macrocells
are registered macrocells with D-type flip-flops, where PA consists of combinatorial
macrocells.
PA Macrocell Structure
Figure 5 shows the PA Macrocell block, which consists of 8 identical combinatorial
macrocells. Each macrocell output can be connected to its own I/O pin on Port A.
There is one user programmable global product term that is output from the GPLD’s
AND ARRAY which is shared by all the macrocells in Port A:
J
PA.OE
Enable or tri-state Port A output pins
The circuit of a PA Macrocell is shown in Figure 6. There are 4 product terms from the
GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the
output, and configure the macrocell to operate as:
J
GPLD Input
Use Port A pin as dedicated input
J
GPLD Output
Use Port A pin as dedicated output
PSD4XXA1
ZPLDBlock
(Cont.)
相關(guān)PDF資料
PDF描述
PSD413A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD412A2-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD412A2-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD412A2-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD412A2-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD412A2-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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