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    參數(shù)資料
    型號: PSD411A2-C-90UI
    廠商: 意法半導(dǎo)體
    英文描述: High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-SOIC -55 to 125
    中文描述: 低成本現(xiàn)場可編程微控制器外圍設(shè)備
    文件頁數(shù): 92/123頁
    文件大?。?/td> 657K
    代理商: PSD411A2-C-90UI
    PSD4XX Famly
    89
    -20
    -25
    ZPLD_TURBO
    OFF
    *
    Symbol
    Parameter
    Conditions
    Min Max Min Max
    Unit
    I/O Input or Feedback to
    Combinatorial Output
    t
    PD
    Port B, E
    55
    80
    Add 20
    ns
    t
    RPD
    Registered Input to
    Combinatorial Output
    (Note 1)
    55
    85
    Add 20
    ns
    t
    EA
    Input to Output Enable
    Any Input
    50
    80
    Add 20
    ns
    t
    ER
    Input to Output Disable
    Any Input
    50
    80
    Add 20
    ns
    t
    ARP
    Register Clear or Preset Delay
    Any Input
    55
    80
    Add 20
    ns
    t
    ARPW
    Register Clear or Preset
    Pulse Width
    Any Input
    30
    60
    ns
    t
    ARD
    Array Delay
    33
    35
    ns
    Combinatorial Delays
    (3.0 V ± 10%)
    13.10 AC/DC Parameters – ZPLDTimng Parameters (ZPSD4XXV Versions)
    (3.0 V ± 10%)
    NOTE:
    1. Port A and latched address from ADIO (A0, A1, A8 – A15).
    -20
    -25
    ZPLD_TURBO
    OFF
    *
    Symbol
    Parameter
    Conditions
    Min
    Max
    Min
    Max
    Unit
    Maximum Frequency
    External Feedback
    1/(t
    S
    + t
    CO
    )
    28.57
    11.11
    MHz
    Maximum Frequency
    Internal Feedback (f
    CNT
    )
    f
    MAX
    1/(t
    S
    +t
    CO
    –10)
    17.24
    12.50
    MHz
    Maximum Frequency
    Pipelined Data
    1/(t
    CH
    + t
    CL
    )
    31.25
    18.52
    MHz
    t
    S
    Input Setup Time
    Any Input
    45
    60
    Add 20
    ns
    t
    H
    Input Hold Time
    Any Input
    0
    0
    0
    ns
    t
    CH
    Clock High Time
    Clock Input
    16
    27
    0
    ns
    t
    CL
    Clock Low Time
    Clock Input
    16
    27
    0
    ns
    t
    CO
    Clock to Output Delay
    Clock Input
    30
    33
    0
    ns
    t
    ARD
    Array Delay for Product
    Term Expansion
    Any Macrocell
    24
    35
    0
    ns
    t
    MIN
    Minimum Clock Period
    t
    CH
    + t
    CL
    30
    30
    0
    ns
    Synchronous Clock Mode
    (3.0 V ± 10%)
    *
    NOTE:
    If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
    相關(guān)PDF資料
    PDF描述
    PSD412A1-C-90UI High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-SOIC -55 to 125
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    PSD403A1-C-15L Low Cost Field Programmable Microcontroller Peripherals
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