參數(shù)資料
型號: PSD402A2-C-15L
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32K X 16 UVPROM, 40 I/O, PIA-GENERAL PURPOSE, CQCC68
封裝: WINDOWED, CERAMIC, LCC-68
文件頁數(shù): 94/123頁
文件大?。?/td> 755K
代理商: PSD402A2-C-15L
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4XX Family
69
APD EN Bit
ALE Power
ALE Status
APD Counter
Down Polarity
0
X
Not Counting
1
X
Pulsing
Not Counting
11
1
Counting (Activates Standby
Mode After 15 Clocks)
10
0
Counting (Activates Standby
Mode After 15 Clocks)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR CLK
ZPLD
APD
ALE PD
*
RCLK
ACLK
TURBO
CMISER
ENABLE
Polarity
1 = OFF
1 = ON
1 = HIGH
PMMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
***
**
Sleep
APD CLK
Mode
1 = ON
1 = CLKIN
PMMR1
Table 18. Power Management Mode Registers (PMMR0, PMMR1)
Table 19. APD Counter Operation
Bit 0 * = Should be set to High (1) to operate the APD.
Bit 1 0 = ALE Power Down (PD) Polarity Low.
1 = ALE Power Down (PD) Polarity High.
Bit 2 0 = Automatic Power Down (APD) Disable.
1 = Automatic Power Down (APD) Enable.
Bit 3 0 = EPROM/SRAM CMiser is OFF.
1 = EPROM/SRAM CMiser is ON.
Bit 4 0 = ZPLD Turbo is ON. ZPLD is always ON.
1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing.
Bit 5 0 = ZPLD Clock Input into the Array from the CLKIN pin input is connected.
Every Clock change will Power Up the ZPLD when Turbo bit is OFF.
1 = ZPLD Clock Input into the Array from the CLKIN pin input is disconnected.
Bit 6 0 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is connected.
1 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is disconnected.
Bit 7 * = In the PSD4XX should be set to High (1)
Bit 0
0 = Automatic Power Down Unit Clock is connected to Port E7 (PE7) alternate
function input.
1 = Automatic Power Down Unit Clock is connected to the PSD Clock
input (CLKIN).
Bit 1
0 = Sleep Mode Disabled.
1 = Sleep Mode Enabled.
Bit 2–7 0 = Reserved for future use, should be set to zero.
The PSD4XX
Architecture
(cont.)
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