• <label id="0p3ux"></label>
    參數(shù)資料
    型號： PSD313-90JM
    廠商： 意法半導(dǎo)體
    英文描述： Current Mode PWM Controller 8-PDIP 0 to 70
    中文描述： 低成本現(xiàn)場可編程微控制器外圍設(shè)備
    文件頁數(shù)： 18/85頁
    文件大?。?/td> 691K
    代理商： PSD313-90JM
    15
    PSD3XX Famly
    10.0
    I/OPort
    Functions
    The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level.
    This permits great flexibility and a high degree of customization for specific applications.
    The next section describes the control registers for the ports. Following that are sections
    that describe each port. Figures 5 through 7 show the structure of Ports A through C,
    respectively.
    Note:
    any unused input should be connected directly to ground or pulled up to V
    CC
    (using a 10K
    to 100K
    resistor).
    10.1 CSIOPORT Registers
    Control of the ports is primarily handled through the CSIOPORT registers. There are 24
    bytes in the address space, starting at the base address labeled CSIOPORT. Since the
    PSD3XX uses internal address lines A15-A8 for decoding, the CSIOPORT space will
    occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to
    reduce wasted address space by connecting lower order address lines (A7 and below)
    to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The
    CSIOPORT space
    must be defined in your PSDsoft design file
    . The following tables list
    the registers located in the CSIOPORT space.
    16-Bit Users Note
    When referring to Table 5B, realize that Ports A and B are still accessible on a byte basis.
    Note: When accessing Port B on a 16-bit data bus, BHE must be low.
    Table 5A. CSIOPORT Registers for 8-Bit Data Busses
    NOTE:
    1. ZPSD only.
    Ofset (in hex)
    fromCSIOPORT
    Base Address
    Type of
    Access
    Allowed
    Register Name
    Port A Pin Register
    Port A Direction Register
    Port A Data Register
    Port B Pin Register
    Port B Direction Register
    Port B Data Register
    Power Management Register (Note 1)
    Page Register
    +2
    +4
    +6
    +3
    +5
    +7
    +10
    +18
    Read
    Read/Write
    Read/Write
    Read
    Read/Write
    Read/Write
    Read/Write
    Read/Write
    Table 5B. CSIOPORT Registers for 16-Bit Data Busses
    NOTE:
    1. ZPSD only.
    Ofset (in hex)
    fromCSIOPORT
    Base Address
    Type of
    Access
    Allowed
    Register Name
    Port A/B Pin Register
    Port A/B Direction Register
    Port A/B Data Register
    Power Management Register (Note 1)
    Page Register
    +2
    +4
    +6
    +10
    +18
    Read
    Read/Write
    Read/Write
    Read/Write
    Read/Write
    相關(guān)PDF資料
    PDF描述
    PSD313-B-70M Current Mode PWM Controller 8-PDIP 0 to 70
    PSD313-B-70U Current Mode PWM Controller 8-PDIP 0 to 70
    PSD313-B-90JI Current-Mode PWM Controller 14-SOIC 0 to 70
    PSD313-B-90LI Current-Mode PWM Controller 8-SOIC 0 to 70
    PSD313-B-90MI Low Cost Field Programmable Microcontroller Peripherals
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD313-90KA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-90LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-90LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-90Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-90QI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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