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    參數(shù)資料
    型號(hào)： PSD313-70JM
    廠商： 意法半導(dǎo)體
    英文描述： Current Mode PWM Controller 16-SOIC 0 to 70
    中文描述： 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
    文件頁(yè)數(shù)： 26/85頁(yè)
    文件大?。?/td> 691K
    代理商： PSD313-70JM
    PSD3XX Famly
    23
    12.0
    Control Signals
    (cont.)
    12.5 A19/CSI
    This pin is configured using PSDsoft to be either a chip select for the entire PSD device or
    an additional PAD input. If your MCU can generate a chip-select signal, and you wish to
    save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic
    input.
    J
    When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD
    in normal operation. However, when a high is detected on the pin, the PSD
    enters Power-down Mode. See Tables 7A and 7B for information on signal states
    during Power-down Mode. See section 16 for details about the reduction of power
    consumption.
    J
    When configured as A19, the pin can be used as an additional input to the PADs.
    It can be used for address or logic. It can also be ALE/AS dependent or a transparent
    input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always
    enabled.
    Port
    Configuration Mode(s)
    State
    AD0–A0/AD15/A15
    All
    MCU I/O
    Tracking AD0/A0-AD7/A7
    Latched Address Out
    MCU I/O
    Chip Select Outputs, CS0–CS7, CMOS
    Chip Select Outputs, CS0–CS7, Open Drain
    Address or Logic Inputs, A16-A18
    Chip Select Outputs, CS8–CS10, CMOS only
    Input (Hi-Z)
    Unchanged
    Input (Hi-Z)
    Logic 1
    Unchanged
    Logic 1
    Hi-Z
    Input (Hi-Z)
    Logic 1
    Port Pins PA0–PA7
    Port Pins PB0–PB7
    Port Pins PC0–PC2
    Table 7A. Signal States During Power-Down Mode
    Internal Signal State
    During Power-Down
    Component
    Internal Signal
    PAD A and PAD B
    CS0–CS10
    Logic 1 (inactive)
    CSADIN, CSADOUT1,
    CSADOUT2, CSIOPORT,
    ES0-ES7, RS0
    Logic 0 (inactive)
    All registers in CSIOPORT
    address space, including:
    Direction
    Data
    Page
    PMR (turbo bit, ZPSD only)
    N/A
    All unchanged
    Table 7B. Internal States During Power-down
    NOTE:
    N/A = Not Applicable
    相關(guān)PDF資料
    PDF描述
    PSD313-90J Low Cost Field Programmable Microcontroller Peripherals
    PSD313-90JI Current Mode PWM Controller 8-PDIP 0 to 70
    PSD313-90JM Current Mode PWM Controller 8-PDIP 0 to 70
    PSD313-B-70M Current Mode PWM Controller 8-PDIP 0 to 70
    PSD313-B-70U Current Mode PWM Controller 8-PDIP 0 to 70
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD313-70LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-70LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-70Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-70QI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
    PSD313-70U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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