- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368145 > PSD301R Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD301R |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，無(wú)的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有12個(gè)輸入） |
| 文件頁(yè)數(shù)： | 18/127頁(yè) |
| 文件大?。?/td> | 682K |
| 代理商： | PSD301R |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)當(dāng)前第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
PSD3XX Famly
2-18
Port A in Non-Multiplexed Address/Data Mode
In this mode, Port A becomes the low order data bus byte of the chip. When reading an
internal location, data is presented on Port A pins. When writing to an internal location, data
present on Port A pins is written to that location.
Port B in Multiplexed Address/Data and in 8-Bit Non-Multiplexed Modes
The default configuration of Port B is I/O. In this mode, every pin can be set as an input or
output by writing into the respective pin’s direction flip flop (DIR FF, in Figure 6). As an
output, the pin level can be controlled by writing into the respective pin’s data flip flop (DFF,
in Figure 6). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0, the pin
is configured as an input. The controller can read the DIR FF bits by accessing the READ
DIR register; it can read the DFF bits by accessing the READ DATA register. Port B pin
levels can be read by accessing the READ PIN register. Individual pins can be configured
as CMOS or open drain outputs. Open drain pins require external pull-up resistors. For
addressing information, refer to Tables 6 and 7.
Alternately, each bit of Port B can be configured to provide a chip-select output signal from
PAD B. PB0–PB7 can provide CS0–CS7, respectively. Each of the signals CS0–CS3 is
comprised of four product terms.Thus, up to four ANDed expressions can be ORed while
deriving any of these signals. Each of the signals CS4–CS7 is comprised of two product
terms. Thus, up to two ANDed expressions can be ORed while deriving any of these
signals.
Port B in 16-Bit Non-Multiplexed Address/Data Mode (PSD30X)
In this mode, Port B becomes the high-order data bus byte of the chip. When reading an
internal high-order data bus byte location, the data is presented on Port B pins. When
writing to an internal high-order data bus byte location, data present on Port B is written to
that location. See Table 9.
Accessing the I/OPort Registers
Tables 6 and 7 show the offset values with the respect to the base address defined by the
CSIOPORT. They let the user access the corresponding registers.
Port C in All Modes
Each pin of Port C (shown in Figure 7) can be configured as an input to PAD A and PAD B
or output from PAD B. As inputs, the pins are named A16–A18. Although the pins are given
names of the high-order address bus, they can be used for any other address lines or logic
inputs to PAD A and PAD B. For example, A8–A10 can also be connected to those pins,
improving the boundaries of CS0–CS7 resolution to 256 bytes. As inputs, they can be
individually configured to be logic or address inputs. A logic input uses the PAD only for
Boolean equations that are implemented in any or all of the CS0–CS10 PAD B outputs. Port
C addresses can be programmed to latch the inputs by the trailing edge ALE or to be
transparent.
Alternately, PC0–PC2 can become CS8–CS10 outputs, respectively, providing the user with
more external chip-select PAD outputs. Each of the signals CS8–CS10 is comprised of one
product term.
ALE/AS and A0–A15 in Non-Multiplexed Modes (PSD3X2/3X3)
In non-multiplexed modes, A0–A15 are address inputs only and can become transparent
(CLOT = 0) or ALE dependent (CLOT = 1). In transparent mode, the ALE/AS pin can be
used as an additional logic input to the PADs. The non-multiplexed ALE dependent mode is
useful in applications for which the host processor has a multiplex address/data bus and
AD0/A0–AD7/A7 are not multiplexed with A0–A7 but rather are multiplexed with other
address lines. In these applications, Port A serves as a data bus and each of its pins can be
directly connected to the corresponding host’s multiplexed pin, where that data bit is
expected. (See Table 8.)
Port Functions
(Cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD304R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD311R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) |
| PSD314R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD302L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD303R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD301R-15J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD301R-15JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD301R-15JM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD301R-20J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD301R-20JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。